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From: teller@cmcl2.NYU.EDU (Patricia J. Teller)
Newsgroups: comp.arch
Subject: TLB consistency on shared-memory MIMD multiprocessors
Message-ID: <16984@cmcl2.NYU.EDU>
Date: Tue, 23-Jun-87 14:24:31 EDT
Article-I.D.: cmcl2.16984
Posted: Tue Jun 23 14:24:31 1987
Date-Received: Thu, 25-Jun-87 02:02:46 EDT
Reply-To: teller@acf3.UUCP (Patricia J. Teller)
Distribution: na
Organization: New York Univsersity
Lines: 3

Does anyone know how TLB consistency is guaranteed on commerical 
Pat Teller (teller@pat.ultra.nyu.edu or teller@cmcl2.arpa)
multiprocessors such as those manufactured by Sequent, Alliant, or Convex?