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From: josh@polaris.UUCP (Josh Knight)
Newsgroups: comp.arch
Subject: Re: Simulation Eats Up MIPS
Message-ID: <858@polaris.UUCP>
Date: Tue, 30-Jun-87 19:55:11 EDT
Article-I.D.: polaris.858
Posted: Tue Jun 30 19:55:11 1987
Date-Received: Sat, 4-Jul-87 13:19:48 EDT
References: <6176@sci.UUCP>
Reply-To: josh@polaris.UUCP (Josh Knight)
Organization: IBM Research, Yorktown Heights, N.Y.
Lines: 20
Keywords: simulation MIPS voracious
Summary: Shouldn't simulation exploit parallel execution?

In article <6176@sci.UUCP> ken@sci.UUCP (Ken Karakotsios) writes:
>
>	There has been some talk that simulation will sink all the MIPs
>that can be thrown at it for a long time to come.  I would tend to agree
>with that.  

Doesn't it seem that this is an arena for special purpose architectures,
perhaps like the YSE or other approaches?  See "The IBM Yorktown Simulation
Engine" (G.F. Pfister, Proc. IEEE, Vol. 74, No. 6, pp. 851-860) for a
description and a fair number of references.  Although it's fairly old
hardware, the article claims a 600-2000 fold speed up over the simulation
rate of a general purpose processor (IBM 370/168).  It seems like logic
simulation is an area with enough inherent parallelism so that using a
traditional SISD machine is just not the right thing to do.

Of course these are only my opinions, not my employers.
-- 

	Josh Knight, IBM T.J. Watson Research
 josh@ibm.com, josh@yktvmh.bitnet,  ...!philabs!polaris!josh