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Path: utzoo!mnetor!seismo!rutgers!sri-spam!mordor!lll-tis!ames!oliveb!intelca!mipos3!ekwok
From: ekwok@mipos3.UUCP (Gibbons V. Ogden)
Newsgroups: comp.lsi,sci.research
Subject: Re: Modelling interconnect
Message-ID: <802@mipos3.UUCP>
Date: Fri, 26-Jun-87 14:23:55 EDT
Article-I.D.: mipos3.802
Posted: Fri Jun 26 14:23:55 1987
Date-Received: Sat, 27-Jun-87 11:39:45 EDT
References: <797@mipos3.UUCP>
Reply-To: ekwok@mipos3.UUCP (Edward C. Kwok)
Organization: Intel CAD, Santa Clara
Lines: 19
Keywords: oops! wrong mail address
Xref: mnetor comp.lsi:163 sci.research:175

In article <797@mipos3.UUCP> ekwok@mipos3.UUCP (Edward C. Kwok) writes:
>
>I would like to know about any ongoing research in circuit models of 
>interconnect, in particular models amenable to automatic extraction from
>layout; i.e. computer recognition of layout structure and transformation 
>of such structure in to discrete/distributed circuit elements. I would
>appreciate if you can give me some pointers, or better still, if you work
>in this area, your willingness to communicate ideas. Thank you much.
>
>My mail path:
>    {the rest of net}!{hplabs,quantel,amdcad,decwrl}!intelca!cadev2!ekwok

should have been:

 {the rest of net}!{hplabs,quantel,amdcad,decwrl}!intelca!mipos3!cadev2!ekwok

sorry.

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