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From: dillon@CORY.BERKELEY.EDU (Matt Dillon)
Newsgroups: comp.sys.amiga
Subject: Re: 68020 Board Wanted
Message-ID: <8706100022.AA07667@cory.Berkeley.EDU>
Date: Tue, 9-Jun-87 20:22:09 EDT
Article-I.D.: cory.8706100022.AA07667
Posted: Tue Jun  9 20:22:09 1987
Date-Received: Fri, 12-Jun-87 05:27:29 EDT
Sender: daemon@ucbvax.BERKELEY.EDU
Lines: 72


	Well, you could make an adapter board yourself without all the
fancy stuff, etc....  Here is the core level signal conversions required
to replace a 68010 with a 68020, and it shouldn't be too different to do it 
with a 68000.  This description is FAR from complete, but should give you
hardware hackers the start you need to do the interface yourself.  Note that
the performance boost will not be all that much, although more than a 68010.
It would be interesting to interface a 25 Mhz 68020 to the Amiga (since the
bus is asyncronous).

				-Matt

68010	68020
socket	processor

CLK	CLK
Vcc	Vcc
Gnd	Gnd
^Reset	^Reset
^Berr	^Berr
^Halt	^Halt
^Br	^Br
^Bg	^Bg
^Bgack	^Bgack
^IPL2	^IPL2
^IPL1	^IPL1
^IPL0	^IPL0
	^IPEND		N.C.
	^ECS		N.C.
	^OCS		N.C.
	^BREN		N.C.
^VPA	^AVEC
E			N.C.
VMA			N.C.
FC0	FC0
FC1	FC1
FC2	FC2
	AD24-31		N.C.
AD23-1	AD23-1
R/^W	R/^W
D15-0	D31-16
	D15-0		N.C.
^DTACK	^DSACK1
	^DSACK0		+5
	^CDIS		+5
	SIZ1		(Note A)
	SIZ0		(Note A)
	A0		(Note A)
	^DS		(Note A)
	^AS		(Note B)
	^RMC		(Note B)


NOTE A:
	A0 and ^DS on the 68020 side are OR'd together to create ^UDS on 
	the 68010 side

	SIZ1, SIZ0, and A0 go into a three input NAND gate with SIZ1 and A0
	inverted beforehand.  The output of the NAND gate becomes the input
	to another OR gate.  The other input to this OR gate is ^DS (all this
	on the 68020 side).  The OUTPUT of the OR gate is the ^LDS signal on
	the 68010 side.


NOTE B:
	^AS and ^RMC are OR'd together to create ^AS on the 68010 side


(Taken from some obscure magazine article dated June 20, 1985).


				-Matt