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From: wingard@ncrcae.Columbia.NCR.COM (Steve Wingard)
Newsgroups: comp.arch,comp.misc,comp.sys.misc
Subject: Re: Info needed on NCR 32/800
Message-ID: <2419@ncrcae.Columbia.NCR.COM>
Date: Mon, 15-Jun-87 09:30:40 EDT
Article-I.D.: ncrcae.2419
Posted: Mon Jun 15 09:30:40 1987
Date-Received: Sun, 21-Jun-87 02:02:06 EDT
References: <220@houxj.UUCP> <219@madhat.UUCP>
Reply-To: wingard@ncrcae.UUCP (Steve Wingard)
Organization: NCR Corp., Engineering & Manufacturing - Columbia, SC
Lines: 19
Xref: mnetor comp.arch:1492 comp.misc:689 comp.sys.misc:640

In article <219@madhat.UUCP> alvitar@madhat.UUCP (Phil Harbison) writes:
>
>The  32/800  uses  both Multibus-I and Multibus-II.  The logical address
>space for each process is 4-Gbytes, split evenly between user and kernel
>space.  The kernel space is further split into 64 subspaces of 32-Mbytes
>each.   One  subspace is allocated for each AP, and one space is divided
>among  the  I/O processors (1-Mbyte each); therefore, any AP can address
>the space of any other AP or I/O processor.
>

Just to clarify a point -- the Tower 32/800 does NOT use Multibus I.
Processor modules have two interfaces on them:  the Multibus II interface
which connects the processor to the rest of the system and a proprietary
interface to the processor's local memory.


Steve Wingard                        ...!ucbvax!sdcsvax!ncr-sd!ncrcae!wingard
NCR Corp., E&M-Columbia              ...!decvax!mcnc!ncsu!ncrcae!wingard
					wingard@ncrcae.NCR.COM