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Path: utzoo!mnetor!seismo!ut-sally!husc6!cmcl2!beta!hc!hi!cyrus
From: cyrus@hi.UUCP (Tait Cyrus)
Newsgroups: comp.sys.nsc.32k
Subject: Re: NS32000 Processor
Message-ID: <8252@hi.UUCP>
Date: Mon, 8-Jun-87 22:08:13 EDT
Article-I.D.: hi.8252
Posted: Mon Jun  8 22:08:13 1987
Date-Received: Thu, 11-Jun-87 05:44:17 EDT
References: <266@udcps1.UUCP>
Reply-To: cyrus@hc.dspo.gov (Tait Cyrus)
Organization: U. of New Mexico, Albuquerque
Lines: 65
Keywords: NS32000 Processor

In article <266@udcps1.UUCP> brian@udcps1.UUCP (Brian R. Haug) writes:
>----------------------------------------------------------------
>32K NEWS                                              April 1987
>    News about the NS32000 processor - Hardware and Software
>     Not affiliated with National Semiconductor Corporation
>----------------------------------------------------------------
> 
>This is the first edition of what we hope will become a forum for 
>the  exchange  of NSC320xx news,  hardware  ideas  and  software.  

Well, I think that this is a good idea, so to get things rolling...

Here at the University of New Mexico, we are building a 5th order 
hypercube (32 node) using the 32032 and 32016.  Each node will contain
the following:

The items marked by a * are things that are different from
anybody elses hypercube.

	1) Compute engine
		a) 32032, (cpu - 32 bit)
		b) 32201, (tcu - timing/control unit)
		c) 32202, (icu - interrupt controller)
		d) 32082, (mmu - memory management unit)
		e) 32081, (fpu - floating point unit)
	     *  f) 8 Megabytes of DRAM
		g) 128  kilobytes of SRAM
	     *  h) running GENIX (Nationals version of 4.2 UNIX)
	2) I/O engine
		a) 32016, (cpu - 16 bit)
		b) 32201, (tcu - timing/controll unit)
		c) 32202, (icu - interrupt controller)
		d) 32082, (mmu - memory management unit)
		e) 32081, (fpu - floating point unit)
		f) 128 kilobytes of SRAM
	     *  g) 2 RS232 ports
	     *  h) ethernet controller (AMD's lance)
	     *  i) SMD disk controller (8466)
	     *  k) 5 ~10 megabytes/sec (1 direction) links

The 8Mbytes of DRAM is sudo-dual ported; that is both processors
can access it.  The 128 kilobytes of SRAM is accessable only by
the local cpu and is used primarily as buffer space for both
the ethernet and disk controllers on the I/O engine and stack space
on the compute engine.

Currently available hypercubes use serial transfers of 10 MegaBITS/sec 
whereas ours will be 16 bit parallel (at ~10 begaBYTES/sec).

Current status:

   We have both of the above wirewrapped on a vme card and are about
to start testing out our hardware design.  After that we will start
to port GENIX.  We hope to have this done in 1-2 months.

-- 
    @__________@    W. Tait Cyrus   (505) 277-0806
   /|         /|    University of New Mexico
  / |        / |    Dept of EECE - Hypercube Project
 @__|_______@  |    Albuquerque, New Mexico 87131
 |  |       |  |
 |  |  hc   |  |    e-mail:
 |  @.......|..@       cyrus@hc.dspo.gov or cyrus@hc.arpa or
 | /        | /        {gatech|ucbvax|convex}!unmvax!hi!cyrus
 @/_________@/