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From: ekwok@mipos3.UUCP (Gibbons V. Ogden)
Newsgroups: sci.research
Subject: Modelling interconnect
Message-ID: <800@mipos3.UUCP>
Date: Fri, 26-Jun-87 13:46:40 EDT
Article-I.D.: mipos3.800
Posted: Fri Jun 26 13:46:40 1987
Date-Received: Sat, 27-Jun-87 11:39:14 EDT
References: <797@mipos3.UUCP
Reply-To: ekwok@mipos3.UUCP (Edward C. Kwok)
Organization: Intel CAD, Santa Clara
Lines: 19


I would like to know about any ongoing research in circuit models of 
interconnect, in particular models amenable to automatic extraction from
layout; i.e. computer recognition of layout structure and transformation 
of such structure in to discrete/distributed circuit elements. I would
appreciate if you can give me some pointers, or better still, if you work
in this area, your willingness to communicate ideas. Thank you much.

My mail path:
    {the rest of net}!{hplabs,quantel,amdcad,decwrl}!intelca!cadev2!ekwok

If you would like to reach out: 408-9877497
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