Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!rutgers!ucla-cs!zen!ucbvax!YMIR.BITNET!NED From: NED@YMIR.BITNET (Ned Freed) Newsgroups: comp.os.vms Subject: Instruction set help file part 3 of 4 Message-ID: <8708100333.AA24306@ucbvax.Berkeley.EDU> Date: Thu, 6-Aug-87 00:41:00 EDT Article-I.D.: ucbvax.8708100333.AA24306 Posted: Thu Aug 6 00:41:00 1987 Date-Received: Mon, 10-Aug-87 04:37:39 EDT Sender: daemon@ucbvax.BERKELEY.EDU Distribution: world Organization: The ARPA Internet Lines: 1402 ==Instruction set help file part 3==cut here==cut here==cut here==cut here== double length and added to the result. The result is then stored in prod. .if manual .s 1 .endif manual Notes: The time listed is for all operands equal to one. If all operands are zero the time is [780-3.00]. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*EXTxV instructions\* .restore .send toc .endif global .else manual 2 EXTxV .endif manual .nf Purpose: extract field - moves bit field to integer .if manual .s 1 .endif manual Format: opcode pos.rl,size.rb,base.vb,dst.wl .if manual .s 1 .endif manual Operation: EXTV: dst = if size NEQU 0 then SEXT ( FIELD (pos, size, base)) else 0 EXTZV: dst = if size NEQU 0 then ZEXT ( FIELD (pos, size, base)) else 0 .if manual .s 1 .endif manual C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = 0 .if manual .s 1 .endif manual Exceptions: Reserved operand .if manual .s 1 .endif manual Opcodes: EE EXTV Extract field, sign extend .index ^Instructions, machine> NEQU kernel then {reserved to Digital opcode fault} else {halt the processor} .if manual .s 1 .endif manual C. Codes: N = 0, Z = 0, V = 0, C = 0 (fault) Unaffected (processor halt) .if manual .s 1 .endif manual Exceptions: Reserved to Digital opcode .if manual .s 1 .endif manual Opcode: 00 HALT Halt .if manual .s 1 .endif manual Description: If process is running in kernel mode, the processor is halted. Otherwise, an opcode reserved to Digital fault occurs. This opcode is 0 to trap many branches to data. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*INCx instructions\* .restore .send toc .endif global .else manual 2 INCx .endif manual .nf Purpose: increment - add 1 to an integer .if manual .s 1 .endif manual Format: opcode sum.mx .if manual .s 1 .endif manual Operation: sum = sum + 1 .if manual .s 1 .endif manual C. Codes: N = {sum LSS 0}, Z = {sum EQL 0}, V = {integer overflow}, C = {carry from MSB} .if manual .s 1 .endif manual Exceptions: Integer overflow .if manual .s 1 .endif manual Opcodes: 96 INCB Increment byte [780-0.40] .index ^Instructions, machine> .if manual .s 1 .endif manual C. Codes: Not affected .if manual .s 1 .endif manual Exceptions: Reserved operand .if manual .s 1 .endif manual Opcode: F0 INSV Insert field [780-3.40] [780-3.51, 750-4.10, 730-14.83] [780F-3.41, 750F-4.10, 730F-14.63] .if manual .s 1 .endif manual Description: The field specified by pos, size and base is replaced by bits {size-1}:0 of src. If size is 0 no action occurs. .if manual .s 1 .endif manual Notes: A reserved operand fault occurs if size GTRU 32 or pos GTRU 31, size NEQU 0 and the field is contained in the registers. On such a fault the condtion codes are unpredictable and the field is left unchanged. The times shown assume all register operands (as is usual for instruction timings). However, if base is changed to a register indexed operand the time is [780-4.00]. All times assume 10 bits extracted starting at bit 4. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*JMP instruction\* .restore .send toc .endif global .index ^Instructions, machine> NEQU 0 then {opcode reserved to Digital fault}; {invalidate per-process translation buffer entries}; {load process general registers from process control block}; {load process map, ASTLVL and PME from PCB}; {save PSL and PC on stack for subsequent REI} .if manual .s 1 .endif manual C. Codes: Not affected .if manual .s 1 .endif manual Exceptions: Reserved operand, privileged instruction .if manual .s 1 .endif manual Opcodes: 06 LDPCTX Load process context .if manual .s 1 .endif manual Description: The process control block is specified by the internal processor register PCBB (process control block base). The general registers are loaded from the PCB, along with the memory management registers describing the address space. The process entries in the translation buffer are cleared. Execution is switched to the kernel stack. The PC and PSL are moved from the PCB to the stack, suitable for use by a REI instruction. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*LOCC instruction\* .restore .send toc .endif global .index ^Instructions, machine> NEQ 0} then {reserved instruction fault}; dst = PRS[procreg] .if manual .s 1 .endif manual C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C C. Codes not affected if destination is not replaced. .if manual .s 1 .endif manual Exceptions: Reserved operand, privileged instruction .if manual .s 1 .endif manual Opcode: DB MFPR Move from processor register .if manual .s 1 .endif manual Description: The specified register is stored in dst. The first operand procreg is a longword that contains the register number. Execution may have register specific side effects. A reserved operand fault can occur if the register does not exist. A reserved instruction fault will occur if MFPR is executed in other than kernel mode. .if manual .send toc .ifnot global .save .flags bold .hl 2 ^*Processor registers\* .restore .send toc .endif global .else manual 3 Processor_registers .endif manual .nf The following table is a summary of the registers accessible in the privileged register space. Each mnemonic can be used to form a symbol by prefixing it with "PR_$__". The number of a register, once assigned, will not change across implementations of the VAX of within an implementation. All unsigned positive number are reserved to Digital, all negative number are reserved for customers. .s 1 The type column indicates whether the register is read-only, write-only, or may be both read and written. The scope column indicates whether the register is maintained on a per-process basis or a per-CPU basis. The init column indicates whether the register is set to some predefined initial value. The dashes mean initialization is optional. .s 1 .if manual .test page 15 .endif manual Register Name Mnemonic Number Type Scope Init ======== ==== ======== ====== ==== ===== ==== Kernel stack pointer KSP 0 R/W PROC --- Executive stack pointer ESP 1 R/W PROC --- Supervisor stack pointer SSP 2 R/W PROC --- User stack pointer USP 3 R/W PROC --- Interrupt stack pointer ISP 4 R/W CPU --- P0 base register P0BR 8 R/W PROC --- P0 length register P0LR 9 R/W PROC --- P1 base register P1BR 10 R/W PROC --- P1 length register P1LR 11 R/W PROC --- System base register SBR 12 R/W CPU --- System length register SLR 13 R/W CPU --- Process control block base PCBB 16 R/W PROC --- System block base SCBB 17 R/W CPU --- Interrupt level IPL 18 R/W CPU yes AST level ASTLVL 19 R/W PROC yes Software interrupt request SIRR 20 W CPU --- Software interrupt summary SISR 21 R/W CPU yes Interval clock control ICCS 24 R/W CPU yes .if manual .test page 12 .endif manual Next interval count NICR 25 W CPU --- Interval count ICR 26 R CPU --- Time of year TODR 27 R/W CPU no Console receiver C/S RXCS 32 R/W CPU yes Console receiver D/B RXDB 33 R CPU --- Console transmit C/S TXCS 34 R/W CPU yes Console transmit D/B TXDB 35 W CPU --- Memory management enable MAPEN 56 R/W CPU yes Trans. buf. inval. all TBIA 57 W CPU --- Trans. buf. inval. single TBIS 58 W CPU --- Performance monitor enable PMR 61 R/W PROC yes System identification SID 62 R CPU no .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*MNEGx instructions\* .restore .send toc .endif global .else manual 2 MNEGx .endif manual .nf Purpose: move the arithmetic negation of a scalar quantity .if manual .s 1 .endif manual Format: opcode src.rx,dst.wx .if manual .s 1 .endif manual Operation: dst = -scr .if manual .s 1 .endif manual C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0 (floating), V = overflow (integer), C = {dst NEQ 0} (integer), C = 0 (floating) .if manual .s 1 .endif manual Exceptions: Integer overflow, reserved operand (floating) .if manual .s 1 .endif manual Opcodes: 8E MNEGB Move negated byte [780-0.40] .index ^Instructions, machine> NEQ 0} then {reserved instruction fault}; PRS[procreg] = src .if manual .s 1 .endif manual C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C C. Codes not affected if register is not replaced. .if manual .s 1 .endif manual Exceptions: Reserved operand, privileged instruction .if manual .s 1 .endif manual Opcode: DA MTPR Move to processor register .if manual .s 1 .endif manual Description: The specified register is loaded. The second operand procreg is a longword that contains the register number. Execution may have register-specific side effects. A reserved operand fault can occur if the register does not exist. A reserved instruction fault will occur if the instruction is executed in other than kernel mode. See the instruction MFPR for a list of processor registers. .if manual .test page 10 .send toc .ifnot global .save .flags bold .hl 1 ^*MULxx instructions\* .restore .send toc .endif global .else manual 2 MULxx .endif manual .nf Purpose: perform arithmetic multiplication .if manual .s 1 .endif manual Format: opcode mulr.rx,prod.mx ;2 operand opcode mulr.rx,muld.rx,prod.wx ;3 operand .if manual .s 1 .endif manual Operation: prod = prod * mulr ;2 operand prod = muld * mulr ;3 operand .if manual .s 1 .endif manual C. Codes: N = {prod LSS 0}, Z = {prod EQL 0}, V = {overflow}, C = 0 .if manual .s 1 .endif manual Exceptions: Integer, floating overflow Floating underflow, reserved operand .if manual .s 1 .endif manual Opcodes: 84 MULB2 Multiply byte 2 operand [780-4.00] .index ^Instructions, machine>