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From: robinson@renoir.Berkeley.EDU (Michael Robinson)
Newsgroups: comp.sys.amiga
Subject: 14.31818 MHz 68010 Upgrade
Message-ID: <19965@ucbvax.BERKELEY.EDU>
Date: Wed, 5-Aug-87 07:14:39 EDT
Article-I.D.: ucbvax.19965
Posted: Wed Aug  5 07:14:39 1987
Date-Received: Sat, 8-Aug-87 01:01:30 EDT
Sender: usenet@ucbvax.BERKELEY.EDU
Reply-To: robinson@renoir.Berkeley.EDU (Michael Robinson)
Distribution: na
Organization: University of California, Berkeley
Lines: 24

I have located part numbers and suppliers for a circuit which will deliver
an exactly doubled, crystal controlled, syncronized clock signal to a 
16MHz 68010 sitting on a daughter board in the processor socket.

This will, in theory, double (plus some) the processor speed of the
Amiga.  To the rest of the system, this will mean the processor will be
making data requests every clock cycle, instead of every other. 

Before I initiate any mutilation, I would like to know what effects this will
have on the various "fast" ram upgrades available.  Presumably, memory 
refresh magic goes on behind the 68000's back during the "off" cycles in
normal operation.  However, do the memory expansions lock out all the 
"off" cycles, or only the ones they need for refresh.  In other words,
if the processor starts requesting data transfer on every system clock,
what percent of the time will it get it?

I would greatly appreciate it if those associated with the manufacture
of the various expansion boards could comment.

Thank you.

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Mike Robinson                                 USENET:  ucbvax!ernie!robinson
                                              ARPA: robinson@ernie.berkeley.edu