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Path: utzoo!utgpu!water!watmath!clyde!cbosgd!gwspc!n8emr!oink!jep
From: jep@oink.UUCP
Newsgroups: comp.sys.att,unix-pc.general
Subject: IMSAI SIO dox
Message-ID: <114@oink.UUCP>
Date: Fri, 14-Aug-87 20:10:49 EDT
Article-I.D.: oink.114
Posted: Fri Aug 14 20:10:49 1987
Date-Received: Sun, 16-Aug-87 08:32:33 EDT
Reply-To: jep@oink.UUCP (James E. Prior)
Distribution: na
Organization: Random Prime Research Institute  Columbus, Ohio
Lines: 24
Keywords: S-100, CP/M, IMSAI, SIO, schematics
Xref: utgpu comp.sys.att:819 junk:5606

IMSAI SIO documentation

Someone posted news requesting documentation for an old IMSAI SIO
board.  I have the dox, but have deleted that old news with the
requestor's identity.  Please send me your address so I can forward
the dox.

Until then, short pins 1&16, 2&15, 3&14, 4&13, 5&12, 7&10, and 8&9 of
sockets A3 and B8 to wire ports as DTEs.  C7 is for a DIP switch: four
pairs of complementary switches.  

a7 pins 1,2,15,16
.
.
.
a4 pins 7,8,9,10

for I/O mapped operation short pins 5&12, and 8&9 of D6.

Baud rate: connect one of pins 1(9600) - 8(110) to both pins 11&12 of B11

My board is a Rev 3

James E. Prior  {ihnp4|cbosgd}!n8emr!oink!jep