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From: john@hpcvlo.HP.COM (John Eaton)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Compaq 386 Bus Speed
Message-ID: <1610028@hpcvlo.HP.COM>
Date: Tue, 11-Aug-87 13:18:26 EDT
Article-I.D.: hpcvlo.1610028
Posted: Tue Aug 11 13:18:26 1987
Date-Received: Sat, 15-Aug-87 01:32:22 EDT
References: <660@hsi.UUCP>
Organization: Hewlett-Packard Co., Corvallis, OR, USA
Lines: 26

<<<<
<
< The static column RAMS have (I think) 50ns access times for addresses
< within the same column, and 100ns for addresses outside that column. The
< 100ns time gives two wait states, the 50ns time gives zero waits.
< Unfortunately, I don't really understand all this.
----------

 It really quite simple. To read a random bit from a Static Column D-ram you 
put the Row address into the ram and strobe RAS. This causes the entire row
to be copied into a buffer. You then put the Column address into the ram and
drop CAS. This selects the bit from the buffer and drives it out. If you
then need any other bits from the same row they are available simply by 
changing the Columnn address. You do not have to repeat the row address.

 In a 32 bit system with 1 Meg rams this gives you a 4 Kbyte cache page using
the buffers that are built into the rams themselves. The first access to a
random location will require wait states but all the rest in that 4K page are
"free". The only problem besides the tendency of programs to seperate their
Code and Data areas is that you have to restrobe RAS after every refresh.
This is not as expensive as a true cache system and will even outrun a true
cache machine if your program has a low enough hit rate.


John Eaton
!hplabs!hp-pcd!john