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From: pete@wlbr.EATON.COM (Pete Lyall)
Newsgroups: comp.sys.m6809
Subject: Re: 512K RAM upgrades
Message-ID: <1107@wlbr.EATON.COM>
Date: Wed, 5-Aug-87 13:15:46 EDT
Article-I.D.: wlbr.1107
Posted: Wed Aug  5 13:15:46 1987
Date-Received: Sat, 8-Aug-87 04:38:40 EDT
References: <AV5EuMy00WAas-w09H@andrew.cmu.edu> <5013@milano.UUCP>
Reply-To: pete@wlbr.UUCP (0000-Pete Lyall)
Organization: Eaton IMS, Westlake Village, CA
Lines: 23

In article <5013@milano.UUCP> baxter@milano.UUCP writes:
>I have had a Performance Peripheral board ......
>...... with the memory acting mostly as cache for a Wini
>disk, 

Ira,

Disk Cache, eh?? Can you elaborate on how it is implemented?? Is
it only cached on the read side (writes go directly do disk for
file system hardening)? Also, is the cache memory usurping precious
system address space (probably not, if you're using the board...).. If
not, how is it getting the memory for the cache allocated to the
driver?? I believe that an OS9 F$srqmem will respond to a device
driver's request with SYSTEM memory. You have my full attention.. I'd
like to hack a similar goody into the GIMIX..

Pete

-- 
                                                   Pete Lyall

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