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From: top@tub.UUCP
Newsgroups: comp.sys.m68k
Subject: Re: mc68020 bra timing? - (nf)
Message-ID: <49400001@tub.UUCP>
Date: Thu, 6-Aug-87 07:31:00 EDT
Article-I.D.: tub.49400001
Posted: Thu Aug  6 07:31:00 1987
Date-Received: Sun, 9-Aug-87 10:21:45 EDT
References: <5930001@hplsla.UUCP>
Lines: 42
Nf-ID: #R:hplsla:5930001:tub:49400001:000:1339
Nf-From: tub!top    Aug  6 12:31:00 1987

>>	Does anyone out there know the 'Best  Case',  'Cache
>>	Case', and 'Worst Case' cycle counts for the MC68020
>>	BRA  instruction.  I can't  seem to  find  it in the
>>	manual.  

>	The "bra" instruction is listed under as Bcc (all
>branches take the same time, regardless of condition;
>bra is just a pseudonym for branch true).
>See section 9.2.15 Conditional Branch Instructions
>in the MC68020 users manual.
>-- 
>Motorola Semiconductor Inc.                Hunter Scales
>Austin, Texas           {ihnp4,seismo,ctvax,gatech}!ut-sally!oakhill!hunter

	First: Nice to hear from a motorola-person.

	Second: Do *YOU* (or anyone else) know any possible
		way to code a loop *WITHOUT* any memory
		references, just cache-references ?

		I thought:

		x: sub.l #1, d0
		   bpl   x

		serves the problem, but I still get one
		memory reference per loop. It seems to
		be the prefetch -- done every loop-cycle
		but thrown away...

It would be nice to here any answers from you motorola-guys out there.
Thanks in advance !

PS: I don't read notes (& mail) that often, so don't wonder if
    it may take some time discussing with me...

Thomas Patzelt, Technical University of Berlin

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