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From: grenley@nsc.nsc.com (George Grenley)
Newsgroups: comp.sys.nsc.32k
Subject: Re: ns32000 processor series
Message-ID: <4532@nsc.nsc.com>
Date: Mon, 3-Aug-87 18:26:42 EDT
Article-I.D.: nsc.4532
Posted: Mon Aug  3 18:26:42 1987
Date-Received: Tue, 4-Aug-87 06:25:38 EDT
References: <777@PSUECLB>
Reply-To: grenley@nsc.UUCP (George Grenley)
Distribution: world
Organization: National Semiconductor, Sunnyvale
Lines: 58

In article <777@PSUECLB> bcd@psueclb.BITNET writes:
>could someone please fill me in the on 32000 processors available these
>days (ie: what features they have, how fast are they etc.)  

Sure.  We make:

32008 - 6,8,10 mhz.  Does not support MMU, but does support FPU.  A part
	for cost sensitive designs

32016 - 6,8,10 mhz.  Does work w/ MMU (32082).  A better choice is
32C16 - 6,10,15 mhz.  CMOS technology, still, you're probably better
	off with a newer part.

32032 - Mainstay of the line.  10 mhz operation, basic 1 MIP machine.

32332 - A definite jump up in performance, 2-2.5 MIPs.  Full 32 bit 
	physical address (the older parts are 24 bit).  When combined
	with 32332 MMU makes a respectable Sun 3 class Unix workstation.

32532 - Our new baby.  Samples due at first of year.  Many, many mips.
	Blocks socks off '020, socks and shoes off '386.  I know how
	fast it is but marketing says I'm supposed to keep my mouth shut.
	But it is fast.  We will offer 20 to 30 mhz clock rates, VAX 8700
	level performance.  Again, as stated, we won't be sampling till
	first of year (it takes TIME to qual a part, guys - you don't
	ship the first wafer to customers, although I realize from your
	end it might seem that way sometimes), but the silicon is coming
	along nicely.  Marketing says they've talked to the press, so
	expect some announcements.

	Let's see, I suppose you'll want some hard facts.  The '532 combines
	the CPU with MMU, and adds Instruction and Data caches.  Since our
	MMU is on chip, we can put the caches on the physical side of the
	bus.  This allows us to add bus watcher logic, to maintain cache
	coherency during times when an external master (like the disk
	controller) is writing data to memory.  Also, since it's a physical
	cache, when you change contexts, you don't have to dump the cache.
	This is a definite advantage over virtual caches.

	Most instructions take 2 clocks, so at 30 meg you're moving right
	along.  (Your mileage may vary).

	Because the caches are relatively large (512 byte I, 1K D), the
	hit rate is about 80%, on real world applications.  This has a
	practical advantage, because as a result, the part is not that
	'sensitive' to external wait states - 1 wait state on every 
	memory cycle only costs about 5%.  Thus, it can be hooked
	directly to DRAM without giving up much - a boon to us harried
	system designers.


Enough.
George Grenley
Nat'l Semiconductor  (well, you didn't think I worked for Intel, did you?)


which are 8, 16, and 32 bit bus interface versions of our 32 bit
architecture.