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From: bill@hpcvlo.HP.COM (Bill Frolik)
Newsgroups: sci.electronics
Subject: Re: TTL Questions
Message-ID: <1090001@hpcvlo.HP.COM>
Date: Tue, 28-Jul-87 13:43:03 EDT
Article-I.D.: hpcvlo.1090001
Posted: Tue Jul 28 13:43:03 1987
Date-Received: Fri, 31-Jul-87 04:26:47 EDT
References: <1395@crash.CTS.COM>
Organization: Hewlett-Packard Co., Corvallis, OR, USA
Lines: 27


>>    2.  I've worked with Schottky and Low-power Schottky logic
>>chips in the lab, and have seen that a no connection to inputs,
>>such as a simple AND or OR gate, even sometimes in MUX's and
>>others, drives the input high.  Is this guaranteed true?   If so,
>>does it apply to all families (S, LS, CMOS, etc.)?  I'm working
>>on projects that would be a heck of a lot easier if this were
>>true.
>
>Never, never, never, never, never assume this! This is the quickest way
>to get into trouble! Yes, standard TTL floats high by nature, but any
>mild strays are enough to glitch it to another state! Generic CMOS doesn't
>float either direction, so it makes a wonderful antenna, and it will couple
>to the subtlest of strays! Since CMOS power glitches when switching, you'd
>like to minimize extraneous switching. This is why you SHOULD tie all inputs
>somewhere, even if they're on gates you're not using!

CMOS devices with floating inputs can cause both the P- and N-channel devices
to be simultaneously on, resulting in a large continuous current through the 
device.  Other gates in the same package may fail to work properly as a 
result of this internal "short".  You should ALWAYS tie all unused inputs
of a CMOS package either high or low.

Bill Frolik
hp-pcd!bill
Hewlett-Packard Portable Computer Division
Corvallis, Oregon  97330