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From: randys@mipon3.intel.com (Randy Steck)
Newsgroups: comp.arch
Subject: MIPS Floating Point processor.
Message-ID: <987@omepd>
Date: Tue, 25-Aug-87 19:00:08 EDT
Article-I.D.: omepd.987
Posted: Tue Aug 25 19:00:08 1987
Date-Received: Fri, 28-Aug-87 00:49:39 EDT
Sender: news@omepd
Reply-To: randys@mipon3.UUCP (Randy Steck)
Distribution: comp.arch
Organization: Intel Corp., Hillsboro
Lines: 28

The August 20 issue of Electronics has an interesting description of the
MIPS floating point processor in their "Technology to Watch" section.  The
implementation looks pretty impressive and I was wonder if someone from
MIPS (John?) could enlighten us on some of the more interesting features
of the part?  

The execution times look very impressive and the fact that the adder,
multiplier, and divider can operate all in parallel could really increase
performance.  However, what sort of algorithm is used to provide a double
precision divide in 5 clocks?

One of the interesting items was the way in which the pipeline of the
processor can be shut down when an exception in one of the floating point
operations is found.  Apparently the instruction stream can be restarted
on the failing instruction.  But, since the execution units operate in
parallel, what happens when a 5 clock multiply is followed by a 2 clock add
and the multiply overflows or signals some other exception?  The add could
have already completed and changed one of the input operands to the previous
multiply so that simply restarting the multiply instruction would not be
sufficient to guarantee the correct result.

Also, do all operations conform to IEEE 754?  This would include rounding
and precision considerations.

All in all, the processor looks very interesting and more detailed
information would be welcome.

Randy Steck  {...intelca!omepd!mipon3!randys}