Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watmath!clyde!rutgers!lll-lcc!pyramid!prls!mips!mash From: mash@mips.UUCP Newsgroups: comp.arch Subject: Re: MIPS Floating Point processor. Message-ID: <629@winchester.UUCP> Date: Thu, 27-Aug-87 01:39:38 EDT Article-I.D.: winchest.629 Posted: Thu Aug 27 01:39:38 1987 Date-Received: Sat, 29-Aug-87 08:20:53 EDT References: <987@omepd> <627@dumbo.UUCP> Reply-To: mash@winchester.UUCP (John Mashey) Distribution: comp.arch Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 40 Keywords: Floating Point, MIPS, R2010 In article <627@dumbo.UUCP> rowen@dumbo.UUCP (Chris Rowen & Mark Johnson) write: > >...The R2010 is a CMOS single chip, closely coupled floating point coprocessor >for the R2000 CPU... The tight handshake between >the two chips handles machine stalls and exceptions without sacrificing >speed or error recovery.... We delay committing state for an instruction >until earlier instructions are known to be exception-free.... A little more, from the software side, on what this means: When we see an FP exception, it's just like any other exception: The exception PC points at the instruction that caused the exception, or to the branch in whose delay slot the faulting instruction lies. Every instruction before the PC has been fully executed; no instruction at the EPC or logically after has had any effect. This area is one where the complexity stayed in the hardware, i.e., we might have had multiple, imprecise exceptions. After I generated the 512 lists to describe what the OS would do with every combination of exceptions, the chippers decided software would NEVER get it all right, so we got precise exceptions instead. (Thank goodness.) Another fact worth mentioning is that the FPU chip is physically LARGER than the CPU chip, even though the CPU has a big TLB, cache control, almost twice as many I/Os, etc. People often ask if we'd put the FPU and CPU together as chip shrinks become available. The usual answer is NO, we'd use more silicon to make an even faster FPU. In the near future (next few shrinks), it seems unlikely that anyone can incorporate a truly high-performance FPU (in the R2010's league) on the same chip as the integer unit. Moral: fast FP uses LOTS of silicon. -- -john mashey DISCLAIMER: UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086