Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watmath!clyde!rutgers!lll-lcc!pyramid!prls!mips!mash From: mash@mips.UUCP Newsgroups: comp.arch Subject: Re: brash micros versus the Big Iron: not yet Message-ID: <630@winchester.UUCP> Date: Thu, 27-Aug-87 02:32:17 EDT Article-I.D.: winchest.630 Posted: Thu Aug 27 02:32:17 1987 Date-Received: Sat, 29-Aug-87 08:35:36 EDT References: <622@winchester.UUCP> <12953@amdahl.amdahl.com> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 30 In article <12953@amdahl.amdahl.com> mat@amdahl.amdahl.com (Mike Taylor) writes: >Model CPUs Cycle "MIPS" > (ns.) MVS Commercial UTS typical >5890-190E 1 15 22 33 >..UTS MIPS are relative performance (throughput capacity) to the VAX-11/780 >arbitrarily defined as 1 MIPS, not measured instruction execution rate. Thanx for the posting! This yields the amusing thought that the 5890 acts like a RISC, according to the (simplistic) MHz/mips ratio: mips MHz MHz/mips CPU / System 2 16.7 8.3 68020 (in Sun-3/160) 5 33 6.6 Fairchild Clipper 4 25 6.2 68020 (in Sun-3/260; caches help) 6 22.2 3.7 VAX 8700 33 66 2.0 Amdahl 5890-190E 10 15 1.5 MIPS M/1000 This is a good illustration of the well-understood fact that you can keep the cycles/mips ratio pretty low, even for a clearly non-RISC architecture. The cost is enough iron to give enough parallelism to permit heavy pipelining. Are the MVS Commercial mips equivalent to the way IBM measures mips? -- -john mashey DISCLAIMER: UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086