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From: reiter@endor.harvard.edu (Ehud Reiter)
Newsgroups: comp.arch
Subject: Pipelining a VAX
Message-ID: <2765@husc6.UUCP>
Date: Thu, 27-Aug-87 10:16:21 EDT
Article-I.D.: husc6.2765
Posted: Thu Aug 27 10:16:21 1987
Date-Received: Sat, 29-Aug-87 09:42:44 EDT
References: <622@winchester.UUCP> <12953@amdahl.amdahl.com> <630@winchester.UUCP>
Sender: news@husc6.UUCP
Reply-To: reiter@harvard.UUCP (Ehud Reiter)
Organization: Aiken Computation Lab Harvard, Cambridge, MA
Lines: 25

In article <630@winchester.UUCP> mash@winchester.UUCP (John Mashey) writes:
>mips	MHz	MHz/mips	CPU / System
>6	22.2	3.7		VAX 8700
>
>This is a good illustration of the well-understood fact that
>you can keep the cycles/mips ratio pretty low, even for a clearly
>non-RISC architecture.

The above figure is a bit misleading, as "mips" on a VAX bear little
relationship to instruction throughput.  About a year ago, I heard a
talk by a DEC engineer who said the instruction throughput on a pipelined VAX
8700 is about one instruction per 8 cycles.  This doesn't seem too impressive,
since the throughput on a non-pipelined VAX-11/780 is one instruction per
10 cycles.  I asked the engineer why they even bothered pipelining if they
only increased the instruction/cycle throughput by 20%, and his response was
that pipelining let them shorten the cycle time (i.e. a pipelined 8700 cycle
does less work than a non-pipelined 780 cycle??).

The above numbers may be a bit off (the talk was a while ago), but it
definitely was the case that the instruction/cycle numbers for the 8700
were only a bit better than the numbers for the 780.

					Ehud Reiter
					reiter@harvard	(ARPA,BITNET,UUCP)
					reiter@harvard.harvard.EDU  (new ARPA)