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From: glg@sfsup.UUCP (G.Gleason)
Newsgroups: comp.arch
Subject: Re: brash micros versus the Big Iron: not yet
Message-ID: <1980@sfsup.UUCP>
Date: Wed, 2-Sep-87 19:45:00 EDT
Article-I.D.: sfsup.1980
Posted: Wed Sep  2 19:45:00 1987
Date-Received: Sat, 5-Sep-87 15:21:43 EDT
References: <622@winchester.UUCP> <12953@amdahl.amdahl.com> <630@winchester.UUCP> <1202@pdn.UUCP> <640@winchester.UUCP> <1221@pdn.UUCP>
Reply-To: glg@/guest4/glgUUCP (xmpj20000-G.Gleason)
Organization: AT&T Information Systems
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In article <1221@pdn.UUCP> alan@pdn.UUCP (0000-Alan Lovejoy) writes:
>There is a fixed cost associated with executing an instruction that has
>nothing to do with how 'simple' or 'complex' it is (the number of bits
>needed to encode the instruction IS important, however).  This argues
>that instructions should perform as much work as possible.

>Instructions that perform a lot of work may do more work than was
>needed, wasting machine resources.  This argues that instructions should
>do as little work as possible.  

In considering why RISC is such a big win, the most important thing is
not so much that complex instructions do more than they have to, but
that implementing them takes more chip area, and therefore slows down
ALL of the instructions.  What makes the RISC processors so fast is that
all this extra chip area is devoted to pipelining, caches, etc.  Since
it turns out that the complex instructions always make up a small
percentage of the executed instructions, and so no matter how much
faster they are, they don't gain much.

Incidentally, instruction size may be important, but not all that
important.  Clearly all the instructions do come in over the bus, and
therefore bus bandwidth can be a limiting factor, but it is not nearly
as important with an internal instruction cache.  One RISC architecture
I have worked with has a cache that holds decoded instructions, which
if you think about it functions a lot like a micro-code store for any
routine that fits in the cache.  Who needs complex instructions or
a micro-store when you have in effect an automatic micro-store.

What the RISC approach represents, is really looking at what costs what,
and putting complexity into the hardware only when this buys you something
significant, not just because it seems like a neat idea.

Gerry Gleason