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From: bobw@wdl1.UUCP (Robert Lee Wilson Jr.)
Newsgroups: comp.arch
Subject: Re: Computers: The New Generation (was: Re: Free Software Foundation)
Message-ID: <3490007@wdl1.UUCP>
Date: Thu, 10-Sep-87 17:01:14 EDT
Article-I.D.: wdl1.3490007
Posted: Thu Sep 10 17:01:14 1987
Date-Received: Sat, 12-Sep-87 15:58:29 EDT
References: <797@spar.SPAR.SLB.COM>
Lines: 20

Concerning the failure rates for DRAMS: There are data available,
from the manufacturers and others, but most present DRAM
configurations for large memories are arranged so that two-bit (and
more) errors come from simultaneous failures in two DRAM chips (or
associated logic) rather than a double bit failure in a single chip.
Most DRAM cips (again I meanas used in for large memories) are 1 bit
wide by 256K or 1M or 4M or .... bits capacity. If your memory design
is n bits wide (including whatever checking bits are used) it
is typically composed of some multiple of n memory chips, in blocks.
In each block are n chips, each holding 1 bit out of 256K (or 1M,
etc.) locations. Thus for the cosmic ray to have a multi-bit effect
it must simultaneously affect several chips, and moe than that must
affect those chips in the same bit locations. That certainly is
possible but it seems less likely than affecting several bits in one
chip, and probability is the central issue when designing codes to
handle different kinds of errors. This appears again when you look
at other singl-point-of-failure possibilities. Since a single
failure in some auxilary logic might easily produce all 1's or all
0's, some ECC schemes are careful to detect those failures as
special cases, even though they are many-bit errors.