Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!mnetor!uunet!husc6!endor!reiter
From: reiter@endor.harvard.edu (Ehud Reiter)
Newsgroups: comp.arch
Subject: Re: Double-bit errors and ECC memory
Message-ID: <2825@husc6.UUCP>
Date: Fri, 11-Sep-87 09:46:28 EDT
Article-I.D.: husc6.2825
Posted: Fri Sep 11 09:46:28 1987
Date-Received: Sat, 12-Sep-87 16:21:34 EDT
References: <1184@itm.UUCP> <797@spar.SPAR.SLB.COM> <2891@phri.UUCP>
Sender: news@husc6.UUCP
Reply-To: reiter@harvard.UUCP (Ehud Reiter)
Organization: Aiken Computation Lab Harvard, Cambridge, MA
Lines: 19

In article <2891@phri.UUCP> roy@phri.UUCP (Roy Smith) writes:
>	Note that the typical-but-mythical memory board described above
>has 7 check bits per 32 bit data word.  Since you need 2N+1 check bits to
>correct an N-bit error, this board should be able to detect and correct as
>many as 3 bad bits in any 32-bit word.

No.  7 check bits will let you correct single-bit errors, and detect double
bit errors.  You would need many more check bits to detect and correct
triple bit errors.

A Hamming code which can correct 1-bit errors and detect 2-bit errors
requires
		ceiling(log2(N)) + 1
check bits, where N is the total number of bits (data + check), i.e. N = 39
if there are 32 data bits and 7 check bits.

					Ehud Reiter
					reiter@harvard	(ARPA,BITNET,UUCP)
					reiter@harvard.harvard.EDU  (new ARPA)