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From: sd@erc3ba.UUCP (S.Davidson)
Newsgroups: comp.arch
Subject: Re: D-machine helped spawn RISC
Message-ID: <347@erc3ba.UUCP>
Date: Fri, 11-Sep-87 08:35:41 EDT
Article-I.D.: erc3ba.347
Posted: Fri Sep 11 08:35:41 1987
Date-Received: Sun, 13-Sep-87 06:42:46 EDT
References: <4782@sdcrdcf.UUCP> <475@esunix.UUCP>
Organization: AT&T ERC, Princeton NJ
Lines: 25
Summary: WISC = VLIW, also coming from microcode.

In article <475@esunix.UUCP>, bpendlet@esunix.UUCP (Bob Pendleton) writes:
> 
> In five years I expect that RISC will be passe, that WISC ( wide instruction
> set computers ) will be all the rage. WISC will be horizontal microcode
> "done right." It will have all the advantages of RISC, but WISC machines will
> run faster and cost less. We haven't abandoned microcode, we've just let it
> out of the closet.
> 
> 		Bob Pendleton
> -- 


It's happened already, though they are not all the rage yet.  They are
called Very Long Instruction Word machines, and one of the originators,
Josh Fisher, did his dissertation on global compaction of horizontal
microcode.  Josh moved to Yale after he graduated, and then moved to a
company to build a VLIW machine.  I don't know the current status of this machine,
though.  At Yale, though, Josh got some very impressive speedups from unrolling
loops and basically running compaction on them, assuming a lot of available resources.
I don't know of any results on real hardware, however.

By the way, I wouldn't say that RISCs are vertical microcode engines done right.
They just include a lot of stuff not necessary in microcode, like direct
addressing and multiplies.  It has never been that hard to generate compilers
for vertical microcode.