Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!seismo!mcvax!ukc!its63b!aiva!richard From: richard@aiva.ed.ac.uk (Richard Tobin) Newsgroups: comp.arch Subject: Re: Computers: The New Generation (was: Re: Free Software Foundation) Message-ID: <163@aiva.ed.ac.uk> Date: Fri, 11-Sep-87 09:25:57 EDT Article-I.D.: aiva.163 Posted: Fri Sep 11 09:25:57 1987 Date-Received: Sun, 13-Sep-87 09:13:57 EDT References: <797@spar.SPAR.SLB.COM> Reply-To: richard@uk.ac.ed.aiva (Richard Tobin) Organization: AI Applications Institute, Edinburgh University Lines: 25 In article <797@spar.SPAR.SLB.COM> hunt@spar.UUCP (Neil Hunt) writes: >Does anyone know about soft failure modes of DRAMs ? How likely >is it to find double bit errors ? With denser and denser memory chips, >one might expect that one day soon, background alpha particles will be >able to flip several adjacent bits. I don't know how likely such adjacent bit errors are, but it shouldn't matter much. Most memory chips are x 1 bit, which means that a given byte will consist of a bit from each of 8 chips. So an error of the kind described will produce correctable 1-bit errors in several adjacent bytes, rather than an uncorrectable multi-bit error in one byte. > Thus 300 Megabytes will get a soft error every > three days or so (bit of a pain !). If this is accurate, it means that a given byte has a 1-in-10^9 chance of getting a single-bit error in a given day, which means the chance of it getting 2 errors in one day (from different alpha particles) is 1-in-10^18 - fairly safe, since to provoke an uncorrectable error, the second bit has to be corrupted before error-correction puts the first one right (this suggests that you should make sure all your physical memory gets read frequently). -- Richard Tobin, JANET: R.Tobin@uk.ac.ed AI Applications Institute, ARPA: R.Tobin%uk.ac.ed@nss.cs.ucl.ac.uk Edinburgh University. UUCP: ...!ukc!ed.ac.uk!R.Tobin