Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!rutgers!im4u!ut-sally!utah-cs!utah-gr!uplherc!esunix!bpendlet From: bpendlet@esunix.UUCP (Bob Pendleton) Newsgroups: comp.arch Subject: Re: D-machine helped spawn RISC Message-ID: <478@esunix.UUCP> Date: Mon, 14-Sep-87 11:33:46 EDT Article-I.D.: esunix.478 Posted: Mon Sep 14 11:33:46 1987 Date-Received: Fri, 18-Sep-87 05:41:40 EDT References: <347@erc3ba.UUCP> Organization: Evans & Sutherland, Salt Lake City, Utah Lines: 69 in article <347@erc3ba.UUCP>, sd@erc3ba.UUCP (S.Davidson) says: - - In article <475@esunix.UUCP>, bpendlet@esunix.UUCP (Bob Pendleton) writes: -- -- In five years I expect that RISC will be passe, that WISC ( wide instruction -- set computers ) will be all the rage. WISC will be horizontal microcode -- "done right." It will have all the advantages of RISC, but WISC machines will -- run faster and cost less. We haven't abandoned microcode, we've just let it -- out of the closet. -- -- Bob Pendleton -- -- - - - It's happened already, though they are not all the rage yet. They are Read my words. Did I say that such machines did not exist? It is hard to make predictions about things that don't exist, easy when things already exist. In fact, such machines have existed for at least 15 years. Recent developments in compiler technology have made them practical for use by people with ordinary budgets. Microcoding has been very expensive. - called Very Long Instruction Word machines, and one of the originators, - Josh Fisher, did his dissertation on global compaction of horizontal A good reference is "Trace Scheduling: A Technique for Global Microcode Compatction" Joseph A. Fisher. IEEE Transactions on Computers, vol. c-30, no. 7, July 1981. By the by, VLIW(TM) and Trace Scheduling(TM) are trademarks of Multiflow Computers, Inc. So I chose to use WISC instead. - microcode. Josh moved to Yale after he graduated, and then moved to a - company to build a VLIW machine. I don't know the current status of this machine, - though. At Yale, though, Josh got some very impressive speedups from unrolling - loops and basically running compaction on them, assuming a lot of available resources. - I don't know of any results on real hardware, however. A good reference is "Bulldog: A Compiler for VLIW Architectures" John R. Ellis MIT Press, 1986 ISBN 262-05034-X The hardware is advertised regularly in Aviation Week & Space Technology. Aviation trad pubs. have lots of computer related info. that some CS types seem to be totally unaware of. - - By the way, I wouldn't say that RISCs are vertical microcode engines done right. - They just include a lot of stuff not necessary in microcode, like direct - addressing and multiplies. It has never been that hard to generate compilers - for vertical microcode. The world YOU live in doesn't need direct addressing and multiplies in microcode. The world I live in requires direct addressing and multiplies, even floating multiplies, in microcode. Out side of your own world, your assumptions do not apply. It has been very hard to write GOOD compilers for horizontal microcode. Please read what I said, not what you wanted me to say. The original article contained references to two key papers in this field. Using anecdotes and rumors to "correct" me is as pointless as my flaming you in this reply. At least I've provided references to cover your anecdotes. Bob P. -- Bob Pendleton @ Evans & Sutherland UUCP Address: {decvax,ucbvax,ihnp4,allegra}!decwrl!esunix!bpendlet Alternate: {ihnp4,seismo}!utah-cs!utah-gr!uplherc!esunix!bpendlet I am solely responsible for what I say.