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From: david@sun.uucp (David DiGiacomo)
Newsgroups: comp.arch
Subject: Re: brash micros versus the Big Iron: not yet
Message-ID: <28093@sun.uucp>
Date: Tue, 15-Sep-87 23:04:52 EDT
Article-I.D.: sun.28093
Posted: Tue Sep 15 23:04:52 1987
Date-Received: Fri, 18-Sep-87 05:43:30 EDT
References: <622@winchester.UUCP> <1980@sfsup.UUCP> <945@edge.UUCP>
Organization: Sun Microsystems, Inc. - Mtn View, CA
Lines: 21

In article <945@edge.UUCP> doug@edge.UUCP (Doug Pardee) writes:
>> In considering why RISC is such a big win, the most important thing is
>> not so much that complex instructions do more than they have to, but
>> that implementing them takes more chip area, and therefore slows down
>> ALL of the instructions.  What makes the RISC processors so fast is that
>> all this extra chip area is devoted to pipelining, caches, etc.
>
>Er, all of this presumes that you're hell-bent on making a single-chip CPU.
>
>We here at Edge make a nice little machine which has a fully 68010
>compatible instruction set, and which executes most instructions in
>one clock cycle (just like them there RISC machines).

I get the impression from recent magazine blurbs that the Edge boxes are
about twice as expensive as RISC systems with similar performance.
Perhaps this is due to the severe cost penalties of multi-{semi-}custom
chip CPU implementation.

Doug, can you provide any cost/performance information?
-- 
David DiGiacomo, Sun Microsystems, Mt. View, CA  sun!david david@sun.com