Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!mit-eddie!ll-xn!ames!aurora!labrea!decwrl!pyramid!prls!mips!mash From: mash@mips.UUCP (John Mashey) Newsgroups: comp.arch Subject: Re: brash micros versus the Big Iron: not yet Message-ID: <687@winchester.UUCP> Date: Wed, 16-Sep-87 13:29:02 EDT Article-I.D.: winchest.687 Posted: Wed Sep 16 13:29:02 1987 Date-Received: Sat, 19-Sep-87 11:44:33 EDT References: <622@winchester.UUCP> <1980@sfsup.UUCP> <945@edge.UUCP> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 18 In article <945@edge.UUCP> doug@edge.UUCP (Doug Pardee) writes: >We here at Edge make a nice little machine which has a fully 68010 >compatible instruction set, and which executes most instructions in >one clock cycle (just like them there RISC machines). 68010 compatible? (was this a typo?) Note: as has been noted earlier in this sequence, you can make most architectures go fast if you throw lots of hardware at them to get more parallelism. VLSI RISC designs are trying to get the performance without burning lots of hardware and $$. -- -john mashey DISCLAIMER: UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086