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From: roy@forbrk.UUCP (Roy Gordon)
Newsgroups: comp.arch
Subject: Re: Spurious Rumours
Message-ID: <372@forbrk.UUCP>
Date: Wed, 16-Sep-87 18:57:08 EDT
Article-I.D.: forbrk.372
Posted: Wed Sep 16 18:57:08 1987
Date-Received: Sat, 19-Sep-87 14:30:50 EDT
References: <10652@orchid.waterloo.edu>
Distribution: comp
Organization: Fortune Systems / SCI Technology  (Berkeley, CA)
Lines: 33

In article <10652@orchid.waterloo.edu> Please don't. writes:
>I've been reading a book (Systems Design with Advanced Microprocessors,
>John Freer, 1987) which mentioned the following in its rundown of 68020
>relatives:
>
>...
> > d)  MC68030  which   integrates  an  MC68020,   a  subset  of  the  MC68851
> > programmable   memory  management   unit  (using  a   22-entry  translation
> > lookahead [sic] buffer) and separate 256-byte  instruction and data caches.

The 68030's PMMU is not a subset of the MC68851.  The 68030's PMMU has
two Transparent Translation Registers (TTR) not found on the 68851.
The registers allow cache hits for an entire range of addresses
for which the logical and physical addresses are the same.

In particular, these registers may be adequate for mapping the Unix
kernel and the i/o space of a system, except for the u-block.
Address hits via the TTR's are cache hits but do not result in
entries in the 68030's 22-entry cache.  In effect, the kernel and
i/o space can now have perfect locality, except for the u-block.

On the 68851 although contiguous addresses can be specified at
high levels of the translation tree, so that lower level page
tables are not needed.  However, each time a page is accessed
within such a space,an entry for that page 
is placed in the translation cache.
The lack of kernel locality will thus result in many
entries in the address translation cache, causing more misses,
more flushes of the cache, etc., etc.

However, limiting the 68030's PMMU address translation cache to
22 entries and no process tag i.d.'s has to be a giant step
backward.