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From: andy@rocky.UUCP
Newsgroups: comp.arch
Subject: Re: D-machine helped spawn RISC
Message-ID: <600@rocky.STANFORD.EDU>
Date: Fri, 18-Sep-87 02:45:28 EDT
Article-I.D.: rocky.600
Posted: Fri Sep 18 02:45:28 1987
Date-Received: Sat, 19-Sep-87 16:00:58 EDT
References: <347@erc3ba.UUCP> <478@esunix.UUCP> <2785@ames.arpa> <6266@apple.UUCP>
Reply-To: andy@rocky.UUCP (Andy Freeman)
Organization: Stanford University Computer Science Department
Lines: 46

In article <6266@apple.UUCP> bcase@apple.UUCP (Brian Case) writes:
>In article <2785@ames.arpa> eugene@pioneer.UUCP (Eugene Miya N.) writes:
>>Added note: the lastest copy of Computer has yet another CISC/RISC
>>debate (this time including Mike Flynn).

>Sigh.

>RISC will become passe as a design fad as soon as something comes along
>to replace the compiler.  In other words, there the "passeness" of RISC
>is nowhere in sight.

Flynn used the same compiler/optimizer with different final code generators
to study a number of different architectures.  (The compiler and optimizer
were written under John Hennessy's direction a few years ago.  Yes, that
Hennessy.)  All of the architectures had the same ALU; they differed in
instruction format and register set architecture.  (They compared different
register window schemes with monolithic register sets of various sizes.)
Since all of the tests used the same compiler and optimizer, much of the
remaining differences were due to differences between the architectures.

One result was that more compact instruction formats were more effective
at reducing instruction traffic than expanding the instruction cache.
``[The 360-like CISC] achieves the same memory performance as [the RISC
architecture], but uses an instruction cache of only half the [RISC]
cache size.''  Flynn, et al argue that this decoding hardware is smaller
than the I-cache necessary for equivalent RISC performance.  Remember,
the critical path in MIPS, MIPS-X, and the Berkeley RISC processors is
not in the control logic; I don't know about MIPS Co's product.

``From data traffic considerations, it seems that the [360-like CISC]
with a register set of about size 16 plus a small data cache is preferable
to multiple register sets for most area combinations.''

Maybe instruction bandwidth isn't important, but data bandwidth seems
to be.  As Flynn and company conclude, ``@i[Balanced optimization] is
the key to overall instruction set efficiency.''  Let's see some data
from RISC folks.

-andy

ps - The article is in the September 87 issue of IEEE Computer.
-- 
Andy Freeman
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