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From: ccplumb@watmath.waterloo.edu (Colin Plumb)
Newsgroups: comp.unix.wizards,comp.arch
Subject: Re: Double-bit errors and ECC memory
Message-ID: <14617@watmath.waterloo.edu>
Date: Thu, 17-Sep-87 01:37:15 EDT
Article-I.D.: watmath.14617
Posted: Thu Sep 17 01:37:15 1987
Date-Received: Sat, 19-Sep-87 18:17:34 EDT
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Reply-To: ccplumb@watmath.waterloo.edu (Colin Plumb)
Organization: U of Waterloo, Ontario
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Confusion: U. of Waterloo, Ontario


In article <9024@ut-sally.UUCP> nather@ut-sally.UUCP (Ed Nather) writes:
>Henry Spencer's suggestion that automatic error correction be included right
>in the memory chip is a good one, but I fear it won't happen soon, if at all.
>We users are so hungry for more memory we put size at a great premium, and
>the chip designers respond. If they are given a choice of more (uncorrected)
>bits vs. fewer (corrected) ones, I doubt they'd choose the latter.  
>
>Chip real estate is expensive: yield is a non-linear function of chip size,
>so tacking ECC manipulations on top of, say, a 4 Mbit memory chip would be
>very costly.  Maybe some day ...

Au contraire!  I forget my sources (trade magazines), but prototype 4 Meg
chips *do* perform ECC.

If your ECC scheme is sophisticated enough, it can handle multi-bit errors,
and thus ignore a hard error (read: flaw in the chip) or two.  Thus, yield
goes *up*.  The only problem is that this circuitry slows the chip down.

One of the fundamental theorems of information theory states that the
number of usable bits on a memory chip can approach, as closely as desired,
the number of good bits there.  (Actually, it's for communication channels,
but the theory applies equally to memory.)  This assumes very sophisticated
ECC and indefinitely large memory chips, but one can do a pretty good job
with 4 Megabits and reasonable timing constraints.

	-Colin Plumb (ccplumb@watmath)

I'll hold the GIRAFFE while you fill the BATHTUB with brightly coloured
MACHINE TOOLS!!