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From: turner@uicsrd.UUCP
Newsgroups: comp.arch
Subject: Re: D-machine helped spawn RISC
Message-ID: <43700023@uicsrd>
Date: Tue, 15-Sep-87 19:49:00 EDT
Article-I.D.: uicsrd.43700023
Posted: Tue Sep 15 19:49:00 1987
Date-Received: Sun, 20-Sep-87 01:24:06 EDT
References: <4782@sdcrdcf.UUCP>
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Nf-ID: #R:sdcrdcf.UUCP:4782:uicsrd:43700023:000:2310
Nf-From: uicsrd.csrd.uiuc.edu!turner    Sep 15 18:49:00 1987


/* Written  9:59 am  Sep 14, 1987 by fay@encore.UUCP in uicsrd:comp.arch */
> 
> Clancy et al. - Proc. Summer 1987 Usenix Conf.) which describes some of
> Multiflow's hardware and software. Truely incredible stuff, if it's for
> real.
> ....
> Normally "conditional jumps occur every five to eight instructions",
> making parallelization very difficult. So simply take a trace of
> normal program execution and have the compiler assume it will USUALLY
> execute that trace.
> ....
> Then compile the new program as if it were not going to take the
> seldom-used branches and plunge ahead.
> ....
> 
> My question to those parllel machine compiler writers out there: is anyone
> writing compilers for non VLIW machines using the same methods? Why can't,
> say, an Alliant-type (or Cedar-type, etc.) machine with hardware lock-step
> between computational elements get a trace execution, recompile assuming
> no branches, and when the 1000th instruction diverts from the "chosen
> path", just back up the CE's and undo the damage?
         ^^^^^^^^^^^^^^^^^^^
> 
> 			peter fay
> 			fay@multimax.arpa
> 
/* End of text from uicsrd:comp.arch */

The problem is one of dynamic vs. static allocation of operations to
functional units.  In a VLIW machine the compiler allocates operations
to functional units at COMPILE time.  The compiler knows which
operations should be undone when an unexpected (unpredicted?)
branch occurs.  In any machine that dynamically allocates iterations
of a loop to CE's it is VERY difficult to determine what operations
must be undone, since an early iteration could branch out of the loop
after some number of other iterations have finished.

Notice that vector operations within a CE are staticly allocated to
the sections of pipe.  So that vector operations could have
conditional branches by allowing 'back up'.  Unless the vector register
length is verry long I have doubts as to the effectiveness of this
however.
---------------------------------------------------------------------------
 Steve Turner (on the Si prairie  - UIUC CSRD)

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