Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!swlabs!jack From: jack@swlabs.UUCP (Jack Bonn) Newsgroups: comp.lang.c Subject: Re: Types Message-ID: <333@swlabs.UUCP> Date: Thu, 3-Sep-87 12:25:24 EDT Article-I.D.: swlabs.333 Posted: Thu Sep 3 12:25:24 1987 Date-Received: Sat, 5-Sep-87 11:42:57 EDT References: <7264@brl-adm.ARPA> <734@sdchema.sdchem.UUCP> <293@osupyr.UUCP> <366@mcdsun.UUCP> Organization: Software Labs, Ltd. Easton CT USA Lines: 62 In article <366@mcdsun.UUCP>, fnf@mcdsun.UUCP (Fred Fish) writes: > In article <320@swlabs.UUCP> jack@swlabs.UUCP (Jack Bonn) writes: > >In article <364@mcdsun.UUCP>, fnf@mcdsun.UUCP (Fred Fish) writes: > >> This only works for jumps to local symbols within the same assembly module, > >> and GREATLY complicates the work of a linker which optimizes both local > >> and global references (since it must now cope with relocation done by > >> the assembler when it inserts or deletes code between the definition and > >> reference of a local symbol). > > > >The algorithm presented requires no such optimization by the linker. The > >assembler described yields object code with the correct long/short jumps and > >no additional relocation/fixup information. > > > >There is nothing for the linker to fixup. > > Sigh, guess we are going to have to go into the gory details. If I understand you correctly, the method I described makes it more difficult for an optimizing linker to do its job. Of course, we had no such optimizing linker (or source thereof), or the assembler optimization would have been unnecessary. But I guess I am troubled by this linker optimization and maybe those in net-land can clarify: 1) Are there many of these optimizing linkers out there? 2) Is it true that to debug in assembler, the listing must be generated after the link is done? I think that this would be necessary since the addresses within the module are changed after the assembly is complete. (Does anyone else use assembler anymore?) 3) What are the consequences on unit testing code that may not match that which is part of the final product. How do we get this past Q/A? (or do we even tell them :-) ) 4) Won't it be true that two identical links may not even be the same length since the orderings in the libraries may change. Won't this make real-time analysis difficult, since the number of bytes of instructions may change from link to link. 5) Has there been any attempt to adjust the ordering of the modules to improve the overall optimization? It seems that this is an analogous situation to that encountered in VLSI placement/layout. Of course this is very computationally intensive for a complex die. But it would make sense to cluster "connected" modules together. Maybe an option to ld is called for, one that pulls object modules from the library _in order_ before trying to resolve unresolved references. At least then, this could be specified manually. Am I the only one who is troubled by all of this? I really like the potential for a automatic mixed model for a "brain-damaged" machine like the one I am posting from (at least for JMPs, calls are trickier). And I am sure there are many things that can be improved by optimizations like this (like the kernel) even for architectures that mix models much more easily than the Intel "family". But I also think that if all tool developers are going to go off and implement an improvement that takes "3 days or so" we might want to take some time and think about the consequences before doing so. -- Jack Bonn, <> Software Labs, Ltd, Box 451, Easton CT 06612 seismo!uunet!swlabs!jack