Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!seismo!rochester!PT!b.gp.cs.cmu.edu!ralf From: ralf@b.gp.cs.cmu.edu (Ralf Brown) Newsgroups: comp.sys.ibm.pc Subject: Re: Switching from Protected to Real Mode Message-ID: <86@b.gp.cs.cmu.edu> Date: Mon, 24-Aug-87 21:22:28 EDT Article-I.D.: b.86 Posted: Mon Aug 24 21:22:28 1987 Date-Received: Wed, 26-Aug-87 00:44:54 EDT References: <1387@imagen.UUCP> <3813@well.UUCP> Organization: Carnegie-Mellon University, CS/RI Lines: 25 Keywords: 286 In article <3813@well.UUCP> johnl@well.UUCP (John A. Limpert) writes: >From what I have heard, they load the IDTR (interrupt descriptor >table register) with 0 and execute an INT 3 instruction. This causes >multiple faults and drops the 80286 back into real mode. I am not >sure what state this leaves you concerning segments and the prefetch >queue. I picked this info up from someone who had gone to one of >the OS/2 seminars. The way I understand it, if another fault occurs after the 286 starts processing a double fault (actually any multiple faults occurring on the same instruction), the 286 goes into the shutdown state. The AT has hardware to issue a reset when the 286 indicates it has entered shutdown. Could this be why the above works? If so, it wouldn't have any advantage over simply toggling the reset line through a MOV AL,0FEh/OUT 64h,AL sequence (and of course you would still have to set the magic flag in CMOS RAM). [the final fault is of course the missing interrupt descriptor table when the 286 tries to invoke the double fault exception handler] -- -=-=-=-=-=-=-=-= {harvard,seismo,ucbvax}!b.gp.cs.cmu.edu!ralf =-=-=-=-=-=-=-=- ARPAnet: RALF@B.GP.CS.CMU.EDU BITnet: RALF%B.GP.CS.CMU.EDU@CMUCCVMA AT&Tnet: (412) 268-3053 (school) FIDOnet: Ralf Brown at 129/31 DISCLAIMER? Who ever said I claimed anything? "I do not fear computers. I fear the lack of them..." -- Isaac Asimov