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From: earl@mips.UUCP (Earl Killian)
Newsgroups: comp.sys.intel,comp.lsi,comp.arch
Subject: Re: 80386 Multiply: quote from Intel
Message-ID: <626@gumby.UUCP>
Date: Wed, 26-Aug-87 15:00:32 EDT
Article-I.D.: gumby.626
Posted: Wed Aug 26 15:00:32 1987
Date-Received: Sat, 29-Aug-87 04:01:16 EDT
References: <576@obiwan.UUCP> <7939@sci.UUCP>
Lines: 20
Xref: mnetor comp.sys.intel:332 comp.lsi:210 comp.arch:1960

In article <357@ohlone.UUCP>, nelson@ohlone.UUCP (Bron Nelson) writes:
> In article <7939@sci.UUCP>, ken@sci.UUCP (Ken Karakotsios) writes:
> > 	By the way, I think you can make this multiplication algorithm
> > work for N bits per clock cycle, if you can provide all the
> > following multiples of one of the inputs (call it Y) : Y, 2Y, ...
> > (2^^N)Y .
> If'n I remember correctly, in fact you need to generate fairly nasty
> values (like 3Y and 5Y) in order to get the 'N' bit modified Booth
> algorithm to work.  This is why you don't typically see orders higher
> than 2 bits.

Oh no, we're about to get another long series of messages saying "X
does Y-bit booth product" just like the "Z has a W-bit word" series.
I doubt that higher order booth products are uncommon.  To illustrate
how unspecial it is (and be the first in the long series :-) let me
point out that even a RISC microprocessor, the MIPS R2000, uses a
3-bit algorithm for integer multiply.  This requires computing 3Y
first, but that's no big deal.  Integer multiply takes 12 cycles.  A
little slow, but acceptable.  At least it's not 33 cycles, as in
architectures with multiply step instructions.