Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!mnetor!uunet!husc6!rutgers!mtune!codas!usfvax2!pdn!alan
From: alan@pdn.UUCP (Alan Lovejoy)
Newsgroups: comp.sys.m68k
Subject: Re: Math, memory chips for 68030
Message-ID: <1206@pdn.UUCP>
Date: Mon, 31-Aug-87 10:37:05 EDT
Article-I.D.: pdn.1206
Posted: Mon Aug 31 10:37:05 1987
Date-Received: Fri, 4-Sep-87 06:46:08 EDT
References: <none> <3792@cit-vax.Caltech.Edu>
Reply-To: alan@pdn.UUCP (0000-Alan Lovejoy)
Organization: Paradyne Corporation, Largo, Florida
Lines: 24
Keywords: 68030 68851 68881

In article <3792@cit-vax.Caltech.Edu> chi@tybalt.caltech.edu (Curt Hagenlocher) writes:
>I  understand that the 68030 has a  subset of the 68851  instructions on
>the chip.  Will the 68030 work with  the 68851?  Or is the subset enough
>to implement all the necessary paging functions?   If not, will Motorola
>be releasing an (updated) version of the 68851 to work with 68030?

>tasks.  Will Motorola be releasing a new math chip with the '030?

The 68851 functionality that is missing from the 68030 mostly concerns
the debugging facilities (i.e., the breakpoint registers).  The memory
management code in an operating system should not be affected by this,
debuggers definitely will be.  I *believe* that the native MMU
functionality of the '030 can be disabled, allowing external devices to
take over this function, but you should probably verify that with
Motorola.

Motorola has announced the 68882 FPU, which has been designed to work
with either the '020 or the '030.  The 68882 will take more advantage
of the parallelism possible with a CPU/FPU system, and will also allow
multiple FPU's to work on the same problem in parallel.  In fact, that
is Motorola's 'graphics coprocessor' strategy:  a board with multiple
68882's working in parallel.

--alan@pdn