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Path: utzoo!dciem!nrcaer!xios!greg
From: greg@xios.XIOS.UUCP (Greg Franks)
Newsgroups: comp.sys.nsc.32k
Subject: Re: what's next???
Message-ID: <355@xios.XIOS.UUCP>
Date: Thu, 27-Aug-87 12:52:34 EDT
Article-I.D.: xios.355
Posted: Thu Aug 27 12:52:34 1987
Date-Received: Sun, 30-Aug-87 07:17:18 EDT
References: <167@unsvax.UUCP> <4538@nsc.nsc.com> <25238@sun.uucp> <585@winchester.UUCP>
Reply-To: greg@sdn.UUCP (Greg Franks)
Organization: XIOS Systems Corporation, Ottawa, Ontario, Canada
Lines: 14

In article <585@winchester.UUCP> mash@winchester.UUCP (John Mashey) writes:
> >6 cycles/vmip].  It's hard to see how the 1-cyle reduction in bus cycles,
>plus the on-chip data cache [whose net benefit is unclear] halve the
>cycles/mips.  

I seem to recall that the 68030 can access the code and data caches
simultaneously (Harvard architecture?).  Perhaps this feature enables
the speed up.


-- 
Greg Franks             XIOS Systems Corporation, 1600 Carling Avenue,
(613) 725-5411          Ottawa, Ontario, Canada, K1Z 8R8
seismo!mnetor!dciem!nrcaer!xios!greg        "Vermont ain't flat!"