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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: comp.unix.wizards,comp.arch
Subject: Re: Double-bit errors and ECC memory
Message-ID: <8587@utzoo.UUCP>
Date: Tue, 15-Sep-87 14:06:20 EDT
Article-I.D.: utzoo.8587
Posted: Tue Sep 15 14:06:20 1987
Date-Received: Tue, 15-Sep-87 14:06:20 EDT
References: <1184@itm.UUCP> <797@spar.SPAR.SLB.COM> <2891@phri.UUCP>, <7319@steinmetz.steinmetz.UUCP>
Organization: U of Toronto Zoology
Lines: 16

Clearly, what we need, urgently, is ECC on the damn memory chips.  There
have already been mutterings about this, but no commercial products as
far as I know.  This is an ideal place for ECC:  wide words are available
internally to reduce the number of correction bits needed (to the extent
that this is desirable -- fewer bits mean poorer coverage against multiple
errors), modest amounts of circuitry are not hard to add, and the problem
with needing read-modify-write cycles for a partial write goes away because
dynamic RAMs have to do this *anyway*.  (Essentially all accesses to DRAMs
are r-m-w cycles, because the internal readout operation is destructive
and must be followed by a writeback, and the chip works internally with
quite large words and *any* write is a partial write, needing a read first.
It's to the credit of DRAM designers that these grubby details are largely
invisible nowadays; high time they did the same for ECC.)
-- 
"There's a lot more to do in space   |  Henry Spencer @ U of Toronto Zoology
than sending people to Mars." --Bova | {allegra,ihnp4,decvax,utai}!utzoo!henry