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From: jpp@slxsys.UUCP (John Pettitt)
Newsgroups: comp.arch
Subject: Re: Double-bit errors and ECC memory
Message-ID: <208@slxsys.UUCP>
Date: Fri, 18-Sep-87 18:21:47 EDT
Article-I.D.: slxsys.208
Posted: Fri Sep 18 18:21:47 1987
Date-Received: Sun, 20-Sep-87 19:57:35 EDT
References: <686@obiwan.UUCP> <8587@utzoo.UUCP>
Reply-To: jpp@slxsys.UUCP (John Pettitt)
Organization: Specialix Systems Ltd, London, U.K.
Lines: 31
Keywords: ram ecc

In article <686@obiwan.UUCP> mark@mips.UUCP (Mark G. Johnson) writes:
>In article <8587@utzoo.UUCP>, henry@utzoo.UUCP (Henry Spencer) writes
>	> Clearly, what we need, urgently, is ECC on the damn memory
>	> chips.  There have already been mutterings about this, but no
>	> commercial products as far as I know.
>Micron Technology's 256Kbit dynamic RAM has on-chip ECC.  And customers
>just frigging HATE the idea.  . . . 
 
>The gripes against ECC are (1) it's "dishonest" because it lets mfrs
>sell defective chips.  {This was also heard three years previously
>when redundant memories were first discussed.}  (2) There's no way to
>tell whether a given chip has a hard error {ECC masks it}, in which
>case the single-bit ECC provides no protection against soft errors.

This may be a dumb suggestion, but ......

Why not have an `ECC_FAULT' pin on the ram chip that signals that
the on chip ecc logic just found and corrected an error ?
This output would then be used to generate a 'ram fault'
signal to the os, and with the correct software place
the service call . . .

This would solve both 1 and 2 above as faulty chips would
be detectable.   This solution seems so simple there must 
be a catch to it but right now I can't see it.


-- 
John Pettitt - G6KCQ, CIX jpettitt, Voice +44 1 398 9422, Discalimer applies ! 
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