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From: aglew@ccvaxa.UUCP
Newsgroups: comp.arch
Subject: Re: D-machine helped spawn RISC
Message-ID: <28200047@ccvaxa>
Date: Sat, 19-Sep-87 18:45:00 EDT
Article-I.D.: ccvaxa.28200047
Posted: Sat Sep 19 18:45:00 1987
Date-Received: Sun, 20-Sep-87 21:09:46 EDT
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Nf-From: ccvaxa.UUCP!aglew    Sep 19 17:45:00 1987


..> Talking about Flynn's article in Computer, CISC vs. RISC,
..> somebody quoted the conclusion that ``A 360-like CISC
..> with 16 registers and a moderate sized data cache''
..> may be the way to go. (paraphrased).

By the way, I am not so sure that you should call a 360-like instruction
set "CISC". The IBM 360 is actually quite a simple machine: a limited
number of instruction formats, fairly regular register use (too few
registers), a limited number of addressing modes...

DON'T FLAME ME, PLEASE!!!! I know all too well the CISCy aspects of the 360:
translate instructions, block moves, and so on - but just want to point out
that, if you subtract a few things, the 360 doesn't look too bad in a RISC
light.
    Of course, RISC began when the IBM 801 group took up where the 360
left off, without marketing pressure to force CISCy kluges...

Flynn is trading off register set size for memory+register->register
operations, both in the context of a simple instruction set. Note that
he is not trading off against all the complicated addressing modes that
a VAX, true CISC, has.
    It isn't written in Stone that a RISC has to be a load-store architecture.
Most are, true, but only because critical evaluation seems to fall on that
side. Flynn examines the alternative...
    I've often thought that RISC might better be described as "Reduced
Addressing Mode Machine", RAMM. In fact, I wrote a paper in an undergrad
course on "RAMM/RISC/SEISM".

After finishing my undergrad course, being all fired up with RISC, I went to
work for a minicomputer manufacturer. While waiting for a US visa, I had
them send up a processor manual. The instruction set looked a lot like a
360 - base register, etc. I wondered what I was getting into.
    But then I mapped out the instruction set and register usage patterns,
and I said to myself "Damn! This machine could run damned fast!" You see,
while it looked like an IBM 360, there weren't very many of the CISCy
features that had been forced upon Amdahl.
    In fact, our CPUs do typically run one instruction per cycle.
Sometimes more.


Andy "Krazy" Glew. Gould CSD-Urbana.    USEnet:  ihnp4!uiucdcs!ccvaxa!aglew
1101 E. University, Urbana, IL 61801    ARPAnet: aglew@gswd-vms.arpa

I always felt that disclaimers were silly and affected, but there are people
who let themselves be affected by silly things, so: my opinions are my own,
and not the opinions of my employer, or any other organisation with which I am
affiliated. I indicate my employer only so that other people may account for
any possible bias I may have towards my employer's products or systems.