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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: comp.arch
Subject: Re: Double-bit errors and ECC memory
Message-ID: <8638@utzoo.UUCP>
Date: Mon, 21-Sep-87 21:45:38 EDT
Article-I.D.: utzoo.8638
Posted: Mon Sep 21 21:45:38 1987
Date-Received: Mon, 21-Sep-87 21:45:38 EDT
References: <686@obiwan.UUCP>, <8637@utzoo.UUCP>
Organization: U of Toronto Zoology
Lines: 12

In a similar vein...  We now have machines that do TLB loading in software
(e.g. MIPSCo) and even an occasional machine that does cache loading in
software (Cheriton's MMUless virtual-address cache).  Has anybody thought
about doing the correction (as opposed to detection) part of ECC in software?
Clearly this is viable only if ECC's purpose is to handle infrequent soft
errors and provide fail-soft behavior in the presence of newly-arrived hard
errors; it won't work if errors are frequent or if you are trying to cover
up rather than fix hard errors.  Given that restriction on its domain of
application, though, it seems like it might work.
-- 
"There's a lot more to do in space   |  Henry Spencer @ U of Toronto Zoology
than sending people to Mars." --Bova | {allegra,ihnp4,decvax,utai}!utzoo!henry