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From: pf@diab.UUCP (Per Fogelstrom)
Newsgroups: comp.unix.wizards,comp.arch
Subject: Re: Double-bit errors and ECC memory
Message-ID: <318@ma.diab.UUCP>
Date: Fri, 18-Sep-87 02:21:48 EDT
Article-I.D.: ma.318
Posted: Fri Sep 18 02:21:48 1987
Date-Received: Thu, 24-Sep-87 00:35:53 EDT
References: <1184@itm.UUCP> <797@spar.SPAR.SLB.COM> <2891@phri.UUCP> <7319@steinmetz.steinmetz.UUCP> <8587@utzoo.UUCP>
Reply-To: pf@ma.UUCP (Per Fogelstrom)
Organization: Diab Data AB, Taby, Sweden
Lines: 10
Xref: mnetor comp.unix.wizards:4400 comp.arch:2293

In article <8587@utzoo.UUCP> henry@utzoo.UUCP (Henry Spencer) writes:
>Clearly, what we need, urgently, is ECC on the damn memory chips.  There
>have already been mutterings about this, but no commercial products as
>far as I know.  This is an ideal place for ECC:  wide words are available
>  [ deleted text ]

There has been an announcment about such a chip. A 1Meg * 1 bit dynamic
cmos ram, with "row error correction" over, i belive 256 bits. Forgive
me if i'm wrong (Can't find that da**ed paper) but i think the
manufacturer was "Samsung".