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From: glg@sfsup.UUCP (G.Gleason)
Newsgroups: comp.arch
Subject: Re: brash micros versus the Big Iron: not yet
Message-ID: <2083@sfsup.UUCP>
Date: Tue, 22-Sep-87 19:01:19 EDT
Article-I.D.: sfsup.2083
Posted: Tue Sep 22 19:01:19 1987
Date-Received: Fri, 25-Sep-87 01:19:15 EDT
References: <622@winchester.UUCP> <1980@sfsup.UUCP> <945@edge.UUCP>
Reply-To: glg@/guest4/glgUUCP (xmpj20000-G.Gleason)
Organization: AT&T Information Systems
Lines: 27

In article <945@edge.UUCP> doug@edge.UUCP writes:
>> In considering why RISC is such a big win, the most important thing is
>> not so much that complex instructions do more than they have to, but
>> that implementing them takes more chip area, and therefore slows down
>> ALL of the instructions.  What makes the RISC processors so fast is that
>> all this extra chip area is devoted to pipelining, caches, etc.

>Er, all of this presumes that you're hell-bent on making a single-chip CPU.

>We here at Edge make a nice little machine which has a fully 68010
>compatible instruction set, and which executes most instructions in
>one clock cycle (just like them there RISC machines).

>No, it doesn't fit on one chip.  More like a dozen.

Don't forget that you get big performance benifits by keeping things on
one chip, since it is expensive in both time and power to drive off chip
loads.  MIPS manages to bury almost all of the memory management overhead
within the normal instruction cycle by putting a translation cache on
the chip.  Also, the next generation of single chip processors will be
very difficult to beat, unless you go to exotic technologies (ie. expensive)

Bus bandwidth is becoming a major bottleneck for most processors, and the
only solution is to eliminate them from the artchitecture, or by shrinking
the circuit so some busses are completely contained on a chip.

Gerry Gleason