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From: alverson@decwrl.UUCP
Newsgroups: comp.arch
Subject: Re: What should be in hardware but isn't
Message-ID: <57@bacchus.DEC.COM>
Date: Thu, 24-Sep-87 02:17:41 EDT
Article-I.D.: bacchus.57
Posted: Thu Sep 24 02:17:41 1987
Date-Received: Sat, 26-Sep-87 09:42:08 EDT
References: <581@l.cc.purdue.edu> <8646@utzoo.UUCP>
Reply-To: alverson@decwrl.UUCP (Robert Alverson)
Organization: Digital Equipment Corporation
Lines: 22

In article <8646@utzoo.UUCP> henry@utzoo.UUCP (Henry Spencer) writes:
>Although you don't get it bundled into one instruction, the pieces needed
>to do this are present in any IEEE floating-point implementation, e.g. the
>68881.  The remainder can be had with one instruction (on the 68881, FMOD
>or FREM depending on exactly what you're doing), the quotient would take
>two I think (just a divide and a convert-to-integer).

Careful now.  FREM gets you the remiander you want.  However, getting the
integer quotient is actually harder.  The problem occurs when the
quotient is larger than an integer.  Often you want the low few bits of
the integer quotient when using FREM to do range reduction.  The last time
I looked the IEEE standard did not provide for these.  However, most chips
give 3 or so of the low end bits, since the designers have actually
thought about why you want FREM.

Overall though, I agree with Henry.  The main reason most of the
complicated instructions mentioned do not show up in RISC's is that
there is no way to express the action in C or Pascal such that the
compiler can reasonably determine to select the complicated instruction
over a sequence of simpler one's.

Bob