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From: marc@CS.UCLA.EDU
Newsgroups: comp.arch,comp.lsi
Subject: VLSI Implementation of ECC
Message-ID: <8348@shemp.UCLA.EDU>
Date: Sat, 26-Sep-87 15:34:00 EDT
Article-I.D.: shemp.8348
Posted: Sat Sep 26 15:34:00 1987
Date-Received: Sun, 27-Sep-87 11:09:18 EDT
Sender: root@CS.UCLA.EDU
Reply-To: marc@CS.UCLA.EDU (Marc Tremblay)
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Organization: UCLA Computer Science Department
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Xref: mnetor comp.arch:2381 comp.lsi:249


	There has been a great deal of discussion lately on Error 
	Correcting Codes. I haven't seen anything on implementation
	issues though. We are presently involved with a couple of
	designs which make use of Hamming code. More specifically,
	I am working on the design of a 32-bit processor with
	fault-tolerance capabilities (CMOS). 

	We use a chain of transmission gates in order to obtain
	the parity bits necessary to encode the Hamming bits.
	The timing is not great but the design is quite simple.

	Does anyone have a fast method for encoding Hamming bits?
	Something in the order of 30ns-40ns for 3 micron technology
	seems like a good target for us.

					Marc Tremblay
					marc@CS.UCLA.EDU
					...!(ihnp4,ucbvax)!ucla-cs!marc
					Computer Science Department, UCLA