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From: peter@sugar.UUCP (Peter da Silva)
Newsgroups: comp.arch
Subject: Re: What should be in hardware but isn't
Message-ID: <826@sugar.UUCP>
Date: Sun, 27-Sep-87 09:27:55 EDT
Article-I.D.: sugar.826
Posted: Sun Sep 27 09:27:55 1987
Date-Received: Wed, 30-Sep-87 00:37:12 EDT
References: <581@l.cc.purdue.edu> <18336@amdcad.AMD.COM> <582@l.cc.purdue.edu> <14750@watmath.waterloo.edu>
Organization: Sugar Land UNIX - Houston, TX
Lines: 17
Summary: TMS 9900

In article <14750@watmath.waterloo.edu>, ccplumb@watmath.waterloo.edu (Colin Plumb) writes:
> In article <582@l.cc.purdue.edu> cik@l.cc.purdue.edu (Herman Rubin) writes:
> >BTW, there is an address modification procedure which is missing on all
> >machines I have seen except the UNIVAC's.  That is to consider the register
> >file as a memory block and allow indexing on it...
> The PDP-10 also did this.  The first 16 memory locations were the registers.
> There was an option to get fast (non-core) memory for these few bits.

The TI 99 processor has something like an address base register, and uses the
next X words of memory as the registers. A standard trick (apparently) is to
map the registers into the I/O page. I think the subroutine call mechanism
involves copying the PC and assigning a new register file. Sort of like a
slow RISC. A very interesting design, anyway.
-- 
-- Peter da Silva `-_-' ...!hoptoad!academ!uhnix1!sugar!peter
--                 'U`  Have you hugged your wolf today?
-- Disclaimer: These aren't mere opinions... these are *values*.