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From: mash@mips.UUCP
Newsgroups: comp.arch
Subject: Re: Demand paged virtual memory (was Re: Free Software Foundation ...)
Message-ID: <724@winchester.UUCP>
Date: Tue, 29-Sep-87 17:53:29 EDT
Article-I.D.: winchest.724
Posted: Tue Sep 29 17:53:29 1987
Date-Received: Fri, 2-Oct-87 00:44:06 EDT
References: <8490@think.UUCP> <1745@ncr-sd.SanDiego.NCR.COM> <819@sugar.UUCP> <6488@brl-smoke.ARPA> <4558@oberon.USC.EDU>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 19

In article <4558@oberon.USC.EDU> blarson@skat.usc.edu (Bob Larson) writes:

>Instruction restart is NOT needed, instruction continuation also works
>quite well.  The 68010 and 68020 both use instruction continuation.  If
>there is strict control of code generation, it is even possible to
>imagine a demand page virtual memory system that does not need either.
>(Preceed each memory reference instruction by an address validity
>check instruction -- I assume this would be used on a RISC processor if
>anywhere.)...
Hmmm.  I don't know anybody who actually does this on a RISC,
but it would be interesting to hear, if so.
Re: continuation versus restart: RISC designs tend to have the
kinds of pipelines that favor restart, although some of the multiple-PC-on-
exception schemes are almost like continuation.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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