Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watmath!clyde!rutgers!iuvax!pur-ee!uiucdcs!uxc.cso.uiuc.edu!ccvaxa!aglew From: aglew@ccvaxa.UUCP Newsgroups: comp.arch Subject: Re: Demand paged virtual memory (was Re Message-ID: <28200051@ccvaxa> Date: Wed, 30-Sep-87 09:36:00 EDT Article-I.D.: ccvaxa.28200051 Posted: Wed Sep 30 09:36:00 1987 Date-Received: Sat, 3-Oct-87 01:29:13 EDT References: <4558@oberon.USC.EDU> Lines: 66 Nf-ID: #R:oberon.USC.EDU:4558:ccvaxa:28200051:000:3093 Nf-From: ccvaxa.UUCP!aglew Sep 30 08:36:00 1987 >/* Written 7:28 pm Sep 28, 1987 by blarson@skat.usc.edu in ccvaxa:comp.arch */ >/* ---------- "Demand paged virtual memory (was Re" ---------- */ >In article <6488@brl-smoke.ARPA> gwyn@brl.arpa (Doug Gwyn (VLD/VMB) ) writes: >>Basically, three things are necessary for full support of demand-paged >>virtual memory: mappable per-process virtual address space pages, >>generation of a trap when a reference is made to an unmapped page, >>and ability to restart the faulted instruction after changing the map. > >Instruction restart is NOT needed, instruction continuation also works >quite well. You think that instruction continuation vs. instruction restart would be a holy war? How about this: neither restart nor continuation of the faulting instruction is necessary. All you have to do is to back up to some consistent state prior to the fault, fetch the page, and then start up before the faulting instruction and steam past it. There have been a whole slew of papers on checkpoint/restart mechanisms recently (cf. Wen-Mei Hwu in CompArch 14). Or you can go whole hog, and say that precise (or micro-precise) page faults aren't necessary at all. Many people are familiar with th Tomasulo algorithm for instruction dispatch: dispatch an instruction as soon as all of its inputs are ready from previous instructions (plus a few extra conditions). Turn this on its head: don't write back the results of an instruction until all previous instructions whose inputs may be modified by this instructions outputs have completed. This will give you imprecise traps, with some instructions in the future having completed before preceding instructions - but it is restartable in the sense that it will not hurt to re-execute those instructions. Eg. in a time sequence of instructions: ....xxxxxxxxddddd--dxxx--xxxPxx------ ^ ^ | LPC | Page Fault | All previous instructions have completed Where x = completed instruction, d = dispatched but not written back, - = not yet started, and P is the page fault Even though the page fault doesnt have precise state, restart at LPC is possible if the Tomasulo condition on writeback is satisfied. --- Berkeley's Kahan, at a recent talk, said that the traditional objection, that imprecise traps are hard to debug, doesn't really apply to his class of problems - or, rather, it already does, because optimizing compilers move his code around so much that he already has imprecise faults. Yet he still manages to produce good, fairly well debugged, code. Andy "Krazy" Glew. Gould CSD-Urbana. USEnet: ihnp4!uiucdcs!ccvaxa!aglew 1101 E. University, Urbana, IL 61801 ARPAnet: aglew@gswd-vms.arpa I always felt that disclaimers were silly and affected, but there are people who let themselves be affected by silly things, so: my opinions are my own, and not the opinions of my employer, or any other organisation with which I am affiliated. I indicate my employer only so that other people may account for any possible bias I may have towards my employer's products or systems.