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From: marc@ucla-cs.UUCP
Newsgroups: comp.arch
Subject: Re: register windows
Message-ID: <8467@shemp.UCLA.EDU>
Date: Sat, 3-Oct-87 13:07:00 EDT
Article-I.D.: shemp.8467
Posted: Sat Oct  3 13:07:00 1987
Date-Received: Sun, 4-Oct-87 02:36:04 EDT
References: <1242@k.gp.cs.cmu.edu>
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Reply-To: marc@CS.UCLA.EDU (Marc Tremblay)
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Organization: UCLA Computer Science Department
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In article <1242@k.gp.cs.cmu.edu> lindsay@k.gp.cs.cmu.edu (Donald Lindsay) writes:
>Register windows interest me.
>
>Lose#1: more state to be saved/restored at task switches. (Caches can
>	be just declared invalid, or have tags.)
>Lose#2: more hardware that can be on the ALU critical path. (Longer R bus,
>	deeper R decode ). 

We designed a register file which almost eliminates this problem. By using
a "Shift-Register File", the data bus only goes through a single window
of registers. In our case it is 16 registers. Adding more windows to 
the file, does not lenghten the data bus. 

>There are some ways to ways to fix things up. For example, instead of a
>call sliding  by (say) 8 registers, slide by a program-supplied distance.
>The average slide might then be (say) 3. This economy helps lose#1, and
>changes lose#2 in very implementation-specific ways. 

To solve some of this problem, we make use of variable-size windows. 
Our windows sizes vary in increments of 4 (8, 12, 16) so that they can
fit a procedure call/return approprietly. In this way very few registers
are wasted because of bigger-than-necessary-windows. That is the reason
while we claim that our file of 64 registers performs just as well
as a normal 128 register file.

For more information you can read:
1) "A Reduced Register File for RISC Architectures", M. Huguet & T. Lang,
    Computer Architecture News (June 1985).
2) "VLSI Implementation of a Shift-Register File", M. Tremblay & T. Lang,
    20th Hawaian Int. Conf. on System Sciences, pp 112-121 (January 1987).

					Marc Tremblay
					marc@CS.UCLA.EDU
					...!(ihnp4,ucbvax)!ucla-cs!marc
					Computer Science Department, UCLA