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From: blu@hall.cray.com (Brain Utterback)
Newsgroups: comp.arch
Subject: Re: What should be in hardware but isn't
Message-ID: <912@hall.cray.com>
Date: Fri, 2-Oct-87 10:51:55 EDT
Article-I.D.: hall.912
Posted: Fri Oct  2 10:51:55 1987
Date-Received: Thu, 8-Oct-87 01:22:29 EDT
References: <581@l.cc.purdue.edu> <18336@amdcad.AMD.COM> <582@l.cc.purdue.edu> <14750@watmath.waterloo.edu> <826@sugar.UUCP>
Reply-To: blu@hall.UUCP (Brian Utterback)
Organization: Cray Research, Inc., Mendota Heights, MN
Lines: 16

In article <826@sugar.UUCP> peter@sugar.UUCP (Peter da Silva) writes:
>In article <14750@watmath.waterloo.edu>, ccplumb@watmath.waterloo.edu (Colin Plumb) writes:
>> In article <582@l.cc.purdue.edu> cik@l.cc.purdue.edu (Herman Rubin) writes:
>> >BTW, there is an address modification procedure which is missing on all
>> >machines I have seen except the UNIVAC's.  That is to consider the register
>> >file as a memory block and allow indexing on it...
>> The PDP-10 also did this.  The first 16 memory locations were the registers.
>> There was an option to get fast (non-core) memory for these few bits.

Another advantage the PDP-10 had by mapping the registers to the memory space, 
other than indexing, was in execution.  You could load a short loop into the
registers and jump to them!  The loop would run much faster, executing out 
of the registers.  
Brian Utterback
Cray Research Inc.
(603) 888-3083