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From: jack@cwi.nl (Jack Jansen)
Newsgroups: comp.arch,comp.unix.wizards,comp.os.minix
Subject: Re: pdp-11/55
Message-ID: <89@piring.cwi.nl>
Date: Wed, 31-Dec-69 18:59:59 EDT
Article-I.D.: piring.89
Posted: Wed Dec 31 18:59:59 1969
Date-Received: Sun, 11-Oct-87 11:46:28 EDT
References: <1755@ncr-sd.SanDiego.NCR.COM> <275@usl> <29933@sun.uucp> <2949@phri.UUCP> <1806@gryphon.CTS.COM> <3019@ames.arpa> <72@bacchus.DEC.COM>
Organization: AMOEBA project, CWI, Amsterdam
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Hmm, I've seen so much misinformation on PDP-11 history by now,
I might as well throw in my own 10 cents of misinformation:

1st generation.
	11/20	Basic pdp-11, no FPU, no MMU, 18 bit unibus (of which
		only 16 were useable).
2nd generation.
	11/45	The first big thing. FPU, MMU (separate I/D), 2 18-bit
		unibusses. The 11/55 seems to be a slightly modified
		version of this thing.
	11/10	Low-end machine. No FPU, no MMU. 18 bit unibus with
		only 16 bits useable. Optional Extended Instruction
		Set that gave you DIV, shift-multiple and some other
		goodies. Also known as 11/05 (OEM) and GT-40 (with
		vector scope)
3rd generation.
	11/40	In between 10 and 45. Optional MMU, optional EIS,
		optional (incompatible) FPU. 18 bit unibus. MMU didn't
		have separate I/D space, no support for instruction
		backup, no PIRQ, no soft SP interrupt, etc. ==11/35.
	11/70	New high-end machine. FPU, MMU (superset of 45 MMU),
		18 bit unibus and 22 (or is it 24?) bit memory bus.
		Massbus (fast bus for mass-storage peripherals). MMU
		had a 'unibus map', so unibus peripherals could reach
		all of memory.
4th generation.
	11/34	Replacement for 11/40. Basically the same thing in
		newer technology, with EIS and MMU standard, and optional
		(11/45 compatible) FPU.
	11/04	11/10 replacement in newer technology.
From now on, things become fuzzy. But, just for your misinformation,
I'll tell what I know, in roughly chronological order.
	11/60	Meant to be new high-end, but failed completely. Very
		fast CPU with user-loadable microcode (but only
		for one or two instructions:-(), MMU, FPU, but only
		18 bit memory bus, and no separate I/D. Grumpf.
	11/780	First VAX. Basically an 11/04 with an extra 32
		bit processor and lots of extra busses. Also slightly
		more expensive.
	11/03	LSI version of 11/04. First Q-bus machine. The Q-bus
		is a poor-mans-unibus: multiplexed A/D lines, only
		one level of interrupts, etc.
	11/23	LSI version of 11/34 with Q-bus.
	11/24	Ditto, only this one had a unibus, a 22 bit memory
		bus and a unibus map.
	11/74	LSI version of 11/70, with qbus.
	11/84	Souped up version of 11/74.
-- 
	Jack Jansen, jack@cwi.nl (or jack@mcvax.uucp)
	The shell is my oyster.